KR960035573A - 8 / 10-bit data converter - Google Patents

8 / 10-bit data converter Download PDF

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Publication number
KR960035573A
KR960035573A KR1019950006851A KR19950006851A KR960035573A KR 960035573 A KR960035573 A KR 960035573A KR 1019950006851 A KR1019950006851 A KR 1019950006851A KR 19950006851 A KR19950006851 A KR 19950006851A KR 960035573 A KR960035573 A KR 960035573A
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KR
South Korea
Prior art keywords
bit
dsv
data
codeword
section
Prior art date
Application number
KR1019950006851A
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Korean (ko)
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KR100207422B1 (en
Inventor
조동일
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019950006851A priority Critical patent/KR100207422B1/en
Publication of KR960035573A publication Critical patent/KR960035573A/en
Application granted granted Critical
Publication of KR100207422B1 publication Critical patent/KR100207422B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
    • H03M7/06—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two
    • H03M7/08—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two the radix being ten, i.e. pure decimal code

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

본 8/10비트 데이터 변환장치는 기록시 재생특성을 고려하여 기록신호의 저역스펙트럼을 줄일 수 있도록 8비트 데이터를 10비트 데이터로 변환제어하는 것이다. 이를 위하여 본 장치는 8비트 입력 데이터 워드 클럭(CLK1)에 따라 8비트 데이터워드를 래치하는 8비트 래치부와: 디지탈 합 편차(DSV)가 -2인 코드워드를 발생빈도가 높은 입력 데이터워드에 대응될 수 있도록 8비트 래치부의 8비트 데이터워드를 10비트 코드워드로 변환하는 데이터 변환부와: 8비트 래치부로부터 출력되는 8비트 데이터워드에 대응하는 10비트코드워드의 DSV의 상태를 검출하는 DSV상태 검출부; 데이터 변환부에서 출력된 10비트 코드워드를 클럭신호(CLK2)에 따라 직렬로 출력하기 위한 10비트 시프트레지스터: 및 데이터 변환부의 10비트 코드워드 중 선두 비트. DSV상태 검출부(30)의 검출결과신호 및 시프트레지스터의 출력비트에 따라 데이터 변환부(20)의 10비트 코드워드 주 선두 비트를 결정하는 DSV 제어부(40)를 포함하도록 구성된다.This 8 / 10-bit data conversion apparatus converts and controls 8-bit data into 10-bit data so that the low spectrum of the recording signal can be reduced in consideration of reproduction characteristics during recording. To this end, the apparatus includes an 8-bit latch unit for latching an 8-bit data word according to the 8-bit input data word clock CLK1: a codeword with a digital sum deviation (DSV) of -2 is input to an input data word having a high frequency. A data conversion section for converting an 8-bit data word of the 8-bit latch section into a 10-bit codeword so as to correspond to: detecting a state of the DSV of the 10-bit code word corresponding to the 8-bit data word output from the 8-bit latch section; A DSV state detector; 10-bit shift register for serially outputting the 10-bit codeword output from the data converter according to the clock signal CLK2; and the first bit of the 10-bit codeword of the data converter. And a DSV control section 40 for determining the 10-bit codeword main head bit of the data conversion section 20 in accordance with the detection result signal of the DSV state detection section 30 and the output bits of the shift register.

Description

8/10 비트 데이터 변환장치8 / 10-bit data converter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 자기 기록에 있어서 8비트 데이터를 10비트 데이터로 변환하는 장치의 일 실시예를 나타낸 회로도이다.1 is a circuit diagram showing an embodiment of an apparatus for converting 8-bit data into 10-bit data in magnetic recording according to the present invention.

Claims (1)

8비트 입력 데이터워드 클럭(CLK1)에 따라 8비트 데이터워드를 래치하는 8비트 래치부와: 디지탈 합 편차(DSV)가 -2인 코드워드를 발생빈도가 높은 입력 데이터워드에 대응될 수 있도록 8비트 래치부의 8비트 데이터워드를 10비트 코드워드로 변환하는 데이터 변환부와: 상기 8비트 래치부로부터 출력되는 8비트 데이터워드에 대응하는 10비트코드워드의 DSV의 상태를 검출하는 DSV상태 검출부; 상기데이터 변환부에서 출력된 10비트 코드워드를 클럭신호(CLK2)에 따라 직렬로 출력하기 위한 10비트 시프트레지스터: 및 데이터 변환부의 10비트 코드워드 중 선두 비트. 상기 DSV상태 검출부(30)의 검출결과신호 및 상기 10비트 시프트레지스터의 출력비트에 따라 상기 데이터 변환부(20)의 10비트 코드워드 주 선두 비트를 결정하는 DSV 제어부(40)를 포함함을 특징으로 하는 8/10비트 데이터 변환장치.An 8-bit latch section for latching the 8-bit dataword in accordance with the 8-bit input dataword clock CLK1, so that a codeword with a digital sum deviation (DSV) of -2 can correspond to an input dataword with a high frequency of occurrence. A data conversion unit for converting an 8-bit data word of the bit latch unit into a 10-bit code word, and a DSV state detection unit for detecting the state of the DSV of the 10-bit code word corresponding to the 8-bit data word output from the 8-bit latch unit; A 10-bit shift register for serially outputting the 10-bit codeword output from the data converter according to the clock signal CLK2; and a first bit of the 10-bit codeword of the data converter. And a DSV controller (40) for determining the 10-bit codeword main head bit of the data converter (20) according to the detection result signal of the DSV state detector (30) and the output bits of the 10-bit shift register. 8 / 10-bit data converter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950006851A 1995-03-29 1995-03-29 8/10 bit data converter KR100207422B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950006851A KR100207422B1 (en) 1995-03-29 1995-03-29 8/10 bit data converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950006851A KR100207422B1 (en) 1995-03-29 1995-03-29 8/10 bit data converter

Publications (2)

Publication Number Publication Date
KR960035573A true KR960035573A (en) 1996-10-24
KR100207422B1 KR100207422B1 (en) 1999-07-15

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Application Number Title Priority Date Filing Date
KR1019950006851A KR100207422B1 (en) 1995-03-29 1995-03-29 8/10 bit data converter

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100590922B1 (en) * 1999-06-30 2006-06-19 비오이 하이디스 테크놀로지 주식회사 LCD frame rate conversion circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100590922B1 (en) * 1999-06-30 2006-06-19 비오이 하이디스 테크놀로지 주식회사 LCD frame rate conversion circuit

Also Published As

Publication number Publication date
KR100207422B1 (en) 1999-07-15

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