KR960032902A - Digital Phase-locked Loop (PLL) - Google Patents

Digital Phase-locked Loop (PLL) Download PDF

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Publication number
KR960032902A
KR960032902A KR1019950003352A KR19950003352A KR960032902A KR 960032902 A KR960032902 A KR 960032902A KR 1019950003352 A KR1019950003352 A KR 1019950003352A KR 19950003352 A KR19950003352 A KR 19950003352A KR 960032902 A KR960032902 A KR 960032902A
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KR
South Korea
Prior art keywords
digital
signal
receiving
loop
oscillated
Prior art date
Application number
KR1019950003352A
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Korean (ko)
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KR0120615B1 (en
Inventor
김영철
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019950003352A priority Critical patent/KR0120615B1/en
Publication of KR960032902A publication Critical patent/KR960032902A/en
Application granted granted Critical
Publication of KR0120615B1 publication Critical patent/KR0120615B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Abstract

디지탈 위상동기루프(Phase Lock Loop : 이하 PLL이라 한다)를 개시한다. 그 디지탈 위상동기루프는 외부로부터의 디지탈신호와 이산발진된 디지탈신호를 입력받아 두 신호의 위상차를 검출하기 위한 디지탈 위상검출 수단과, 상기 검출된 위상차 신호를 입력받아 소정 루프 계수에 따라 루프 필터링하기 위한 디지탈 루프필터수단과, 상기 루프 필터링된 신호를 입력받아 증폭하기 위한 디지탈 증폭수단 및 상기 증폭된 신호를 입력받아 상기 이산 발진된 디지탈신호를 출력하는 이산발진수단을 구비한다. 따라서, 회로의 단순화가 가능하며, 소비전력을 줄일 수 있다.A digital phase locked loop (hereinafter referred to as PLL) is started. The digital phase-locked loop receives digital signals and discretely oscillated digital signals from the outside, and digital phase detection means for detecting phase differences between the two signals, and loop-filtered according to a predetermined loop coefficient by receiving the detected phase difference signals. Digital loop filter means for receiving, digital amplification means for receiving and amplifying the loop filtered signal and discrete oscillation means for receiving the amplified signal and outputs the discrete oscillated digital signal. Therefore, the circuit can be simplified, and power consumption can be reduced.

Description

디지탈 위상동기루프(PLL)Digital Phase Synchronous Loop (PLL)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 디지탈 위상동기루프(PLL)를 도시한 블럭도이다.1 is a block diagram showing a digital phase locked loop (PLL) according to the present invention.

Claims (2)

외부로부터의 디지탈신호와 이산발진된 디지탈신호를 입력받아 두 신호의 위상차를 검출하기 위한 디지탈 위상검출수단; 상기 검출된 위상차 신호를 입력받아 소정 루프 계수에 따라 루프 필터링하기 위한 디지탈 루프 필터수단; 상기 루프 필터링된 신호를 입력받아 증폭하기 위한 디지탈 증폭수단; 및 상기 증폭된 신호를 입력받아 상기 이산 발진된 디지탈신호를 출력하는 이산발진수단을 구비한 것을 특징으로 하는 디지탈 위상동기루프.Digital phase detection means for receiving a digital signal and a discretely oscillated digital signal from the outside and detecting a phase difference between the two signals; Digital loop filter means for receiving the detected phase difference signal and performing loop filtering according to a predetermined loop coefficient; Digital amplifying means for receiving and amplifying the loop filtered signal; And discrete oscillating means for receiving the amplified signal and outputting the discretely oscillated digital signal. 제1항에 있어서, 상기 이산발진수단은 상기 증폭된 신호와 자체 발진된 신호(Pnom)를 가산하는 제1가산수단; 상기 제1가산수단의 출력과 궤환된 계단파형(Fout)의 신호를 가산하는 제2가산수단; 및 상기 제2가산수단의 출력을 입력받아 상기 계단파형(Fout)의 신호를 출력하는 레지스터를 구비한 것을 특징으로 하는 디지탈 위상동기루프.2. The apparatus of claim 1, wherein the discrete oscillating means comprises: first adding means for adding the amplified signal and the self oscillated signal Pnom; Second adding means for adding an output of the first adding means and a signal of the stepped waveform Fout fed back; And a register for receiving the output of the second adding means and outputting the signal of the step waveform (Fout). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950003352A 1995-02-21 1995-02-21 Digital pll KR0120615B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950003352A KR0120615B1 (en) 1995-02-21 1995-02-21 Digital pll

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950003352A KR0120615B1 (en) 1995-02-21 1995-02-21 Digital pll

Publications (2)

Publication Number Publication Date
KR960032902A true KR960032902A (en) 1996-09-17
KR0120615B1 KR0120615B1 (en) 1997-10-30

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ID=19408529

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950003352A KR0120615B1 (en) 1995-02-21 1995-02-21 Digital pll

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KR (1) KR0120615B1 (en)

Also Published As

Publication number Publication date
KR0120615B1 (en) 1997-10-30

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