KR930018869A - Circuits and Methods for Generating Clock Signals Dynamically - Google Patents

Circuits and Methods for Generating Clock Signals Dynamically Download PDF

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KR930018869A
KR930018869A KR1019930002221A KR930002221A KR930018869A KR 930018869 A KR930018869 A KR 930018869A KR 1019930002221 A KR1019930002221 A KR 1019930002221A KR 930002221 A KR930002221 A KR 930002221A KR 930018869 A KR930018869 A KR 930018869A
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South Korea
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signal
frequency
input
control
amplified
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KR1019930002221A
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Korean (ko)
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KR100231810B1 (en
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이. 글래든 마이클
피. 라비오레트 윌리암
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빈센트 비. 인그라시아
모토로라 인코포레이티드
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Microcomputers (AREA)

Abstract

클럭 발생기(30)는 고주파 혹은 저주파 발진기에 응답하여 시스템 클럭을 동적으로 발생한다. 증폭된 발진 입력은 멀티플렉서(62), 분할기(56) 및, 비교회로(58,60)의 제1입력에 제공된다. 분할기(56)는 발진 입력 주파수를 분할하여 분할된 입력을 멀티플렉서(62)의 제2입력에 제공한다. 비교회로(58,60)는 상기 입력 주파수를 기준 주파수와 비교하여, 상기 입력 주파수가 하이(high)인지 로(low)인지를 결정한다.The clock generator 30 dynamically generates a system clock in response to a high frequency or low frequency oscillator. The amplified oscillation input is provided to the multiplexer 62, divider 56 and first inputs of the comparison circuits 58 and 60. The divider 56 divides the oscillation input frequency and provides the divided input to the second input of the multiplexer 62. Comparing circuits 58 and 60 compare the input frequency with a reference frequency to determine whether the input frequency is high or low.

상기 입력 주파수가 로이라면, 멀티플렉서(62)는 인에이블되어 상기 시스템 클럭으로서 상기 발진 입력을 제공한다. 부가적으로, 비교 회로(58,60)는 증폭기(50)를 인에이블시키기 위한 제어 신호를 제공하여, 상기 입력 주파수에 따라서 고이득 인자 혹은 저이득 인자를 이용하여, 상기 발진기 입력을 증폭한다.If the input frequency is low, multiplexer 62 is enabled to provide the oscillation input as the system clock. Additionally, comparison circuits 58 and 60 provide a control signal for enabling amplifier 50 to amplify the oscillator input using either a high gain factor or a low gain factor depending on the input frequency.

Description

클럭 신호를 동적으로 발생하는 회로 및 방법Circuits and Methods for Generating Clock Signals Dynamically

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의한 실시예에 따른 집적 회로 데이타 프로세서를 설명하는 블럭도.1 is a block diagram illustrating an integrated circuit data processor in accordance with one embodiment of the present invention.

제2도는 제1도의 데이타 프로세서의 클럭 발생기를 설명하는 부분 블럭도.FIG. 2 is a partial block diagram illustrating the clock generator of the data processor of FIG.

제3도는 제2도의 클럭 발생기의 발진 발생 및 증폭기(an oscillator generator and amplifier)를 설명하는 부분 블럭도.FIG. 3 is a partial block diagram illustrating an oscillator generator and amplifier of the clock generator of FIG.

제4도는 제3도의 발진 발생 및 증폭기의 증폭기를 설명하는 회로도.4 is a circuit diagram illustrating the oscillation generation and amplifier of the amplifier of FIG.

Claims (4)

제1주파수의 제1기준 신호와 제2주파수의 제2기준신호를 수신하여 제1클럭 신호를 제공하는 집적회로 크럭신호 발생기에 있어서, 상기 제1기준 신호를 수신, 증폭하여 증폭된 신호를 제공하는 증폭수단; 상기 증폭 수단에 접속되어 제3주파수를 갖는 제2클럭 신호를 제공하기 위해, 상기 증폭된 신호를 처리하는 제1논리수단;상기 제2 기준 신호를 수신하기 위한 제1입력과, 상기 증폭된 신호를 수신하기 위한 제2입력을 구비하고, 상기 증폭된 신호와 제2기준 신호 각각을 처리하여 제1제어 신호를 제공하는 제어수단 및; 상기 증폭수단, 제1논리수단 및, 제어수단에 접속되어, 상기 제1제어 신호에 응답하여 상기 제1주파수 혹은 제3주파수로 상기 제1클럭 신호를 제공하는 선택수단; 을 부가적으로 구비하는 직접 회로 클럭 신호발생기.An integrated circuit clock signal generator for receiving a first reference signal of a first frequency and a second reference signal of a second frequency and providing a first clock signal, wherein the first reference signal is received and amplified to provide an amplified signal. Amplification means; First logic means for processing the amplified signal to provide a second clock signal having a third frequency connected to the amplifying means; a first input for receiving the second reference signal and the amplified signal A control means having a second input for receiving a signal, and processing the amplified signal and the second reference signal to provide a first control signal; Selection means connected to said amplifying means, first logic means, and control means for providing said first clock signal at said first or third frequency in response to said first control signal; Integrated circuit clock signal generator further comprising. 제1주파수의 제1클럭 신호 발생방법에 있어서, 제2주파수의 제1기준 신호를 수신하는 단계, 상기 제2주파수로 증폭된 신호를 제공하기 위해, 소정의 이득 인자에 의해 상기 제1기준 신호를 증폭하는 단계, 상기 제2주파수보다 작은 제3주파수로 분할된 신호를 제공하기 위해, 상기 증폭된 신호의 제2주파수를 분할하는 단계, 제1제어신호를 제공하기 위해 제4주파수를 갖는 제2기준 신호와, 상기 제2주파수를 갖는 상기 제1기준 신호를 비교하는 단계 및, 상기 제1제어 신호 값에 응답하여 상기 제2주파수 혹은 제3주파수로, 상기 제1클럭 신호를 제공하는 단계,를 구비하는 제1주파수의 제1클럭 신호를 발생하는 방법.A method of generating a first clock signal of a first frequency, the method comprising: receiving a first reference signal of a second frequency, to provide a signal amplified by the second frequency, by using a predetermined gain factor; Amplifying a signal, dividing a second frequency of the amplified signal to provide a signal divided into a third frequency smaller than the second frequency, and a fourth having a fourth frequency to provide a first control signal. Comparing a second reference signal with the first reference signal having the second frequency, and providing the first clock signal at the second frequency or the third frequency in response to the first control signal value; And generating a first clock signal of a first frequency. 발진기 입력에 응답하여 시스템 클럭 신호를 수신하기 위한 제1입력, 분할된 시스템 클릭 신호를 수신하기 위한 제2입력신호를 갖고, 상기 기준 신호와 상기 분할된 시스템 클럭 신호들 사이의 차이를 나타내는 에러 신호를 제공하는 비교기;상기 에러신호를 수신하고, 제1제어 신호를 제공하는 필터 수단; 상기 제1제어 신호에 응답하여 상기 시스템 클럭 신호를 제공하는 전압 제어된 발진 수단;상기 시스템 클럭 신호를 분할하여, 상기 비교기의 제2입력으로 상기 분할된 시스템클럭 신호를 제공하는 분할 수단을 구비한 위상 룩 루프 회로에 있어서, 증폭된 신호를 제공하기 위해 상기 발진 입력을 수신증폭하는 증폭수단; 상기 증폭 수단에 접속되어, 제1클럭 신호를 제공하기 위해 상기 증폭된 신호를 처리하는 제1논리수단; 상기 시스템 클럭 신호를 수신하기 위한 제1입력과, 상기 증폭된 신호를 수신하기 위한 제2입력을 갖고, 제2제어 신호를 제공하기 위해 상기 증폭된 신호와 상기 시스템 클럭 신호 각각을 처리하는 제어수단; 상기 증폭 수단, 제1논리 수단, 제어수단에 접속되어, 상기 제2제어신호에 응답하여 상기 시스템 클럭 신호로서, 상기 증폭된 신호 혹은 상기 제1클럭 신호를 제공하는 멀티플렉서로 이루어지는 클록 발생 수단을 구비한 것을 특징으로 하는 위상 록 루프 회로.An error signal having a first input for receiving a system clock signal in response to an oscillator input, a second input signal for receiving a divided system click signal, and indicating a difference between the reference signal and the divided system clock signals Comparator for providing; Filter means for receiving the error signal, and provides a first control signal; Voltage controlled oscillation means for providing said system clock signal in response to said first control signal; dividing means for dividing said system clock signal and providing said divided system clock signal to a second input of said comparator; 11. A phase look loop circuit comprising: amplifying means for receiving and amplifying said oscillating input to provide an amplified signal; First logic means connected to said amplifying means for processing said amplified signal to provide a first clock signal; Control means having a first input for receiving the system clock signal and a second input for receiving the amplified signal and processing each of the amplified signal and the system clock signal to provide a second control signal ; Clock generation means connected to said amplification means, first logic means, and control means, said clock generation means comprising a multiplexer for providing said amplified signal or said first clock signal as said system clock signal in response to said second control signal; A phase lock loop circuit, characterized in that. 집적 회로 클럭 신호 발생기에 있어서, 출력을 가진 발진기, 상기발진기에 접속된 제1입력과, 또한 출력을 갖는 분할기, 상기 증폭기에 접속된 제1입력과, 상기분할기에 접속된 제2입력과, 외부 제어 신호에 접속된 제3입력과, 또한 출력을 갖는 클럭 제어 회로, 상기 클럭 제어 회로에 접속된 제1입력과, 상기 외부 제어 신호에 접속된 제2입력과, 또한 출력을 갖는 주파수 검출기 및, 상기 증폭기에 접속된 제1입력과, 상기분할기에 접속된 제2입력과, 상기 주파수 검출기에 접속된 제3입력과, 또한 출력을 갖는 멀티플랙서, 를 구비한 집적 회로 클럭 신호 발생기.An integrated circuit clock signal generator, comprising: an oscillator having an output, a first input connected to the oscillator, a divider having an output, a first input connected to the amplifier, a second input connected to the splitter, and an external device A frequency control having a third input connected to the control signal, a clock control circuit having an output, a first input connected to the clock control circuit, a second input connected to the external control signal, and also having an output; And a multiplexer having a first input connected to the amplifier, a second input connected to the splitter, a third input connected to the frequency detector, and an output. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930002221A 1992-02-18 1993-02-18 Cluck signal actuating circuit and method KR100231810B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/835,834 US5155451A (en) 1992-02-18 1992-02-18 Circuit and method for dynamically generating a clock signal
US835,834 1992-02-18

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KR930018869A true KR930018869A (en) 1993-09-22
KR100231810B1 KR100231810B1 (en) 1999-12-01

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JP2917731B2 (en) 1999-07-12
US5155451A (en) 1992-10-13
JPH0685666A (en) 1994-03-25
KR100231810B1 (en) 1999-12-01
EP0556597A1 (en) 1993-08-25

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