KR940023019A - Clock distribution circuit - Google Patents

Clock distribution circuit Download PDF

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Publication number
KR940023019A
KR940023019A KR1019930003206A KR930003206A KR940023019A KR 940023019 A KR940023019 A KR 940023019A KR 1019930003206 A KR1019930003206 A KR 1019930003206A KR 930003206 A KR930003206 A KR 930003206A KR 940023019 A KR940023019 A KR 940023019A
Authority
KR
South Korea
Prior art keywords
clock
phase
distribution
output signal
controlled oscillator
Prior art date
Application number
KR1019930003206A
Other languages
Korean (ko)
Other versions
KR950008955B1 (en
Inventor
황승회
이준
박원우
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930003206A priority Critical patent/KR950008955B1/en
Publication of KR940023019A publication Critical patent/KR940023019A/en
Application granted granted Critical
Publication of KR950008955B1 publication Critical patent/KR950008955B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

본 발명은 클럭 분배회로를 공개한다. 그 회로는 압력되는 제1클럭을 위상 동기 루프로 동기를 맞추어 안정화시켜 낮은 스큐출력이 되도록하여 위상 및 주파수를 검출하는 위상/주파수 검출수단, 상기 위상/주파수 검출수단의 출력신호의 지터를 방지하기 위한 루프 필터, 상기 루프 필터의 출력신호를 전압 제어 발진하기 위한 전압 제어 발진기, 상기 전압 제어 발진기의 출력신호를 입력하여 클럭을 분배하고 제어하거나 테스트 클럭이나 테스트 인에이블 클럭을 입력하여 클럭을 분배하고 제어하기 위한 분배 및 제어수단, 선택신호에 응답하여 상기 분배 및 제어수단의 신호를 선택적으로 출력하기 위한 클럭선택 수단을 구비하고 있다. 따라서, 다양한 클럭신호를 발생할 수 있으며 원칩으로 집적화하여 면적을 최소화하고 다양한 시스템에의 적용이 가능하며 스큐 및 지연시간을 줄일 수 있다.The present invention discloses a clock distribution circuit. The circuit comprises a phase / frequency detection means for detecting phase and frequency by synchronizing and stabilizing the first clock under pressure in a phase locked loop to achieve a low skew output, and to prevent jitter in the output signal of the phase / frequency detection means. Inputs a loop filter, a voltage controlled oscillator for voltage-controlled oscillation of the output signal of the loop filter, an output signal of the voltage-controlled oscillator, and distributes and controls a clock or inputs a test clock or a test enable clock to distribute a clock. Distribution and control means for controlling, and clock selection means for selectively outputting signals of the distribution and control means in response to a selection signal. Therefore, various clock signals can be generated and integrated into one chip to minimize the area, to be applied to various systems, and to reduce skew and delay time.

Description

클럭 분배 회로Clock distribution circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 클럭 분배회로의 블럭도를 나타내는 것이다. 제3도는 본 발명의 클럭 분배회로를 이용한 일실시예의 시스템을 나타내는 것이다.2 shows a block diagram of the clock distribution circuit of the present invention. 3 shows a system of an embodiment using the clock distribution circuit of the present invention.

Claims (2)

입력되는 제1클럭과 동기를 맞추어 위상 및 주파수를 검출하는 위상/주파수 검출수단; 상기 위상/주파수 검출수단의 출력신호의 지터를 방지하기 위한 루프 필터; 상기 루프 필터의 출력신호를 전압 제어 발진하기 위한 전압 제어 발진기; 상기 전압 제어 발진기의 출력신호를 입력하여 클럭을 분배하고 제어하거나 테스트 클럭이나 테스트 인에이블 클럭을 입력하여 클럭을 분배하고 제어하기 위한 분배 및 제어수단; 선택신호에 응답하여 상기 분배 및 제어수단의 신호를 선택적으로 출력하기 위한 클럭선택 수단을 구비한 것을 특징으로 하는 클럭 분배회로.Phase / frequency detection means for detecting phase and frequency in synchronization with the input first clock; A loop filter for preventing jitter of the output signal of the phase / frequency detection means; A voltage controlled oscillator for voltage controlled oscillation of the output signal of the loop filter; Distribution and control means for distributing and controlling a clock by inputting an output signal of the voltage controlled oscillator or distributing and controlling a clock by inputting a test clock or a test enable clock; And clock selection means for selectively outputting signals of said distribution and control means in response to a selection signal. 제1항에 있어서, 상기 분배 및 제어수단은 상기 전압제어 발진기의 클럭신호에 응답하여 클럭신호를 분배하여 출력하거나 테스트 클럭신호에 응답하여 클럭신호를 분배하여 테스트를 수행하는 것을 특징으로 하는 클럭 분배회로.The clock distribution apparatus of claim 1, wherein the distribution and control unit distributes and outputs a clock signal in response to a clock signal of the voltage controlled oscillator or distributes a clock signal in response to a test clock signal. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930003206A 1993-03-04 1993-03-04 Clock distributer KR950008955B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930003206A KR950008955B1 (en) 1993-03-04 1993-03-04 Clock distributer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930003206A KR950008955B1 (en) 1993-03-04 1993-03-04 Clock distributer

Publications (2)

Publication Number Publication Date
KR940023019A true KR940023019A (en) 1994-10-22
KR950008955B1 KR950008955B1 (en) 1995-08-09

Family

ID=19351614

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930003206A KR950008955B1 (en) 1993-03-04 1993-03-04 Clock distributer

Country Status (1)

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KR (1) KR950008955B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000001111A (en) * 1998-06-08 2000-01-15 김영환 CLOCK SIGNAL distributor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100808079B1 (en) * 2005-09-16 2008-03-03 후지쯔 가부시끼가이샤 Clock signal generating and distributing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000001111A (en) * 1998-06-08 2000-01-15 김영환 CLOCK SIGNAL distributor

Also Published As

Publication number Publication date
KR950008955B1 (en) 1995-08-09

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