KR950008955B1 - Clock distributer - Google Patents

Abstract

The circuit comprises a phase/frequency detecting unit which detects the phase and the frequency of first clock, a loop filter which filters the output signals from the phase/frequency detecting unit, a voltage controlling generator which generates and controls the voltage of the output signals from the loop filter, a clock distributing unit which selects one of the clock signal and test clock signal from the generator to distribute in some ratio, and a clock selecting unit which selects one of the clock signals from the clock distributing unit in order to output.

Description

Clock distribution circuit

1 shows a block diagram of a conventional clock distribution circuit.

2 shows a block diagram of the clock distribution circuit of the present invention.

3 shows a system of an embodiment using the clock distribution circuit of the present invention.

* Explanation of symbols for main parts of the drawings

100: phase / frequency detector 200: boost and loop filter

300: voltage controlled oscillator 400: input means

500: clock distribution and control means 600: clock selection means

The present invention relates to a clock distribution circuit, and more particularly, to a clock distribution circuit in a system operating at a high speed.

When designing a system board that operates at a high speed by using a high frequency clock signal between 50 MHz and 100 MHz, command and data are exchanged according to the central processing window and the clock signals input to several ICs. However, the central processing unit and several ICs require different set-up and hold times according to each IC when data is inputted, and time variables are set based on the clock signal to be input. In order to control such a time variable, the skew and delay time between high speed clock signals allocated to each IC should be minimized to increase or decrease according to the actually defined variable value. The circuit for controlling this time variable is a clock distribution circuit.

1 shows a block diagram of a conventional clock distribution circuit.

The block distribution circuit shown in FIG. 1 is a clock distribution means for generating a clock signal of xMHz and a clock distribution means for generating a clock signal of xMHz and x / 2MHz by inputting a signal from the clock generating means (10). 20, the central processing unit 30 performing the operation in synchronization with the clock signal of the clock distribution means 20, IC1 performing the operation in synchronization with the clock signal of the clock distribution means 20 x / 2MHz (40), delay means (50) for delaying the clock signal of x2MHZ of clock distribution means (20) and IC1 (40) for performing operation in synchronization with the clock signal of x / 2MHZ delayed by delay means (50). It is. In addition, the clock distribution means 20 simultaneously performs a function of converting the ECL into a TTL. In addition, when clocks of various frequencies are required, a plurality of two-dividing circuits may be additionally used to divide the two-divided signals into two separate portions. In addition, when the set-up and hold times of the central processing window 30 and the associated ICs do not coincide, the clock is delayed by using an external delay means. In addition, when the fan-out of the clock distribution means is not sufficient, a buffer is connected and used.

Therefore, in the conventional clock distribution circuit, first, an external two-division circuit and a plurality of two-division circuits are added during high-speed system operation to increase the skew and delay time between the supplied clocks, thereby adjusting the correct time variable. it's difficult.

Second, it is difficult to obtain a clock of a desired frequency band only by adding an external circuit when a synchronization clock of various frequencies is required.

Third, when the fan-out is not sufficient, the error increases because it is difficult to predict the time variable by using the transistor-transistor logic buffer.

Accordingly, it is an object of the present invention to provide a clock distribution circuit that can easily obtain clocks of various frequencies and minimize skew and delay time between clocks.

In order to achieve the above object, the clock distribution circuit according to the present invention is a phase / frequency detection means for detecting the phase and frequency of the first clock by stabilizing and synchronizing the first clock with the phase-locked loop to achieve a low skew output. Inputs a loop filter to filter the output signal of the phase / frequency detection means to prevent jitter, a voltage controlled oscillator for voltage-controlled oscillation of the output signal of the loop filter, and an output signal of the voltage-controlled oscillator to distribute and control the clock, or test Clock distribution means for inputting a clock or a test enable signal to distribute and control the clock, and clock selection means for selectively outputting the clock output from the clock distribution means in response to the selection signal.

Hereinafter, a clock distribution circuit according to the present invention will be described with reference to the accompanying drawings.

2 shows a block diagram of the clock distribution circuit of the present invention.

The clock distribution circuit shown in FIG. 2 has an output of a phase / frequency detector 100 and a phase / frequency detector 100 for inputting a synchronous clock SYNC CLK and a feedback clock FB CLK to detect phase and frequency. A loop filter 200 for filtering and boosting the signal to prevent jitter, a voltage controlled oscillator 300 for voltage-controlled oscillation of the output signal of the loop filter 200, a test clock TCLK or a test enable signal TESTEN; By inputting the output signal of the voltage controlled oscillator 300 from the input means 400 and the input means 400 for inputting the output signal of the voltage controlled oscillator 300, the clock is distributed and controlled, or the test clock TCLK or A clock distribution means (500) for inputting and controlling a clock by inputting a test enable signal (TESTEN), and a clock selection means for selectively outputting a clock output from the clock distribution means (500) in response to a programmed selection signal ( 600).

Operation of one embodiment according to the above configuration is as follows.

The input synchronization clock SYNC CLK is stabilized by synchronizing with the phase synchronization loop PLL of the phase / frequency detector 100 so as to have a low skew value. In addition, the phase-locked loop PLL lines up the positive edges of the synchronous clock SYNC CLK and the feedback clock FB CLK, that is, the synchronous clock SYNC CLK and the feedback clock FB CLK. By feeding back the clock with the same phase, the associated output clock can be matched to the input sync clock.

The loop filter 200 filters and boosts the output signal of the phase / frequency detector 100 to prevent jitter in the output signal.

The output signal of the loop filter 200 of the voltage controlled oscillator 300 is a voltage controlled oscillation, and operates up to 300 MHz.

The input unit 400 inputs a test clock TCLK or a test enable signal TESTEN and an output signal of the voltage controlled oscillator 300 and supplies them to the clock distribution means 500. On the other hand, the test enable signal TESTEN and the test clock TCLK are inputted instead of the clocks of the synchronous clock SYNC CLK and the voltage controlled oscillator 300 to check whether the clock distribution means 500 performs the operation without error. .

The clock distribution means 500 inputs the output signal of the voltage controlled oscillator 300 to distribute and control the clock, or inputs the test clock TCLK or the test enable signal TESTEN to distribute and control the clock. It operates as shown in Table 1 below.

TABLE 1

The operation of Table 1 is a table showing the operation under the assumption that the control by two bits. At this time, the bit can be extended.

In Table 1, f denotes an internal phase-locked loop frequency of the phase / frequency detector 100, mode 0 is the case where the frequency of OUT0 and the frequency of OU1 are the same ratio, and mode 1 is the frequency of OUT0 and the frequency of OUT1. Is a ratio of 3: 2, and mode 2 is a case where the frequency of OUT0 and the frequency of OUT1 are a ratio of 2: 1.

The clock selection means 600 is for selectively outputting the clock output from the clock distribution means 500 in response to the programmed selection signals PSEL 0 to PSEL M, and operates as shown in Table 2 below.

TABLE 2

The operation of Table 2 is a table showing the operation under the assumption that the control by two bits. At this time, the bit can be extended.

3 shows a system of an embodiment using the clock distribution circuit of the present invention.

The system shown in FIG. 3 assumes that the central processing unit 700 operates at 100 MHz, the interface chips 701 and 702 operate at 50 MHz, and the LAN and SCSI controllers 703 and 704 operate at 25 MHz. . First, set the CSEL stage to 10, and OUTA = 100MHz

Output clocks with OUTB = 50MHz, OUTC = 25MHz, and OUTD = 12.5MHz. The skew and delay time between them can be minimized by the one-chip of the cooler distribution means 705, and the set-up time and the hold time can be compensated for by the external circuit during the synchronous operation of each chip.

Accordingly, the clock distribution circuit of the present invention may first generate clock signals of various frequencies in the same clock distribution circuit, thereby reducing skew and delay time between clocks.

Secondly, it can be supplied to a chip operating synchronously at desired frequencies.

Third, the central processing unit of the system board can be modularized so that only the central processing unit can be replaced according to the frequency, thereby diversifying the product.

Fourth, the area occupied by the seed can be minimized by enabling one-chip application to all products.

Claims (1)

Phase / frequency detection means for synchronizing and stabilizing the inputted first clock with an internal phase synchronization loop so as to have a low skew value, and detecting phase and frequency of the first clock; A boost and loop filter for filtering and boosting the output signal of the phase / frequency detection means to prevent jitter of the output signal; A voltage controlled oscillator for voltage controlled oscillation of the output signal of the loop filter; Clock distribution means for selecting one of an output clock signal and a test clock signal of the voltage controlled oscillator according to a first selection signal and distributing it at a predetermined ratio; And clock selection means for selecting and outputting one of clock signals distributed and output from the clock distribution means in response to a second selection signal.