KR960032676A - Method of manufacturing device isolation oxide film of semiconductor device - Google Patents

Method of manufacturing device isolation oxide film of semiconductor device Download PDF

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KR960032676A
KR960032676A KR1019950003909A KR19950003909A KR960032676A KR 960032676 A KR960032676 A KR 960032676A KR 1019950003909 A KR1019950003909 A KR 1019950003909A KR 19950003909 A KR19950003909 A KR 19950003909A KR 960032676 A KR960032676 A KR 960032676A
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forming
film
oxide film
semiconductor substrate
device isolation
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KR1019950003909A
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KR100324813B1 (en
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엄금용
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체소자의 소자분리 산화막의 제조방법에 관한 것으로서, 반도체 기판상에 질소 뎅글링 본드막을 형성하고, 소자분리 영역으로 예정되어 있는 부분을 노출시키는 중첩되어진 패드산화막과 다결정 실리콘층 및 질화막 패턴을 형성한 후, 상기 패턴들 양측의 반도체기판에 트랜치를 형성하고, 열산화공정을 실시하여 소자분리 산화막을 형성하였으므로, 질소 뎅글링 본드막에 의해 패드산화막 패턴으로의 산소 침투가 방지되어 버즈빅의 크기가 작아지며, 반도체기판의 스트레스가 완충되어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a device isolation oxide film of a semiconductor device, the method including forming a nitrogen dangling bond film on a semiconductor substrate and exposing a predetermined portion as a device isolation region, an overlapped pad oxide film, a polycrystalline silicon layer, and a nitride film pattern. After forming the trenches, trenches were formed in the semiconductor substrates on both sides of the patterns, and a thermal oxidation process was performed to form a device isolation oxide film. The size of the circuit board is reduced, and the stress of the semiconductor substrate is buffered, thereby improving process yield and reliability of device operation.

Description

반도체소자의 소자분리 산화막 제조방법Method of manufacturing device isolation oxide film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 및 제2B도는 본 발명에 따른 반도체소자의 소자분리 산화막 제조 공정도2A and 2B are process diagrams for fabricating a device isolation oxide film of a semiconductor device according to the present invention.

Claims (13)

반도체기판상에 질소 뎅글링 본드막을 형성하는 공정과, 상기 질소 뎅글링 본드막상에 패드산화막을 형성하는 공정과, 상기 패드산화막상에 다결정실리콘층을 형성하는 공정과, 상기 다결정실리콘층 상에 질화막을 형성하는 공정과, 상기 반도체기판에서 소자분리영역으로 예정되어 있는 부분 상측의 질화막에서 질소 뎅글링 본드막까지를 순차적으로 제거하여 반도체기판을 노출시키는 질화막과 다결정실리콘층과 패드산화막 및 질소 뎅글링 본드막 패턴을 형성하는 공정과, 상기 질화막 패턴 양측의 반도체기판에 예정된 깊이의 트랜치를 형성하는 공정과, 상기 반도체기판을 열산화시켜 소자분리 산화막을 형성하는 공정을 구비하는 반도체소자의 소자분리 산화막의 제조방법Forming a nitrogen dangling bond film on the semiconductor substrate, forming a pad oxide film on the nitrogen dangling bond film, forming a polysilicon layer on the pad oxide film, and a nitride film on the polysilicon layer And a nitride film, a polycrystalline silicon layer, a pad oxide film, and a nitrogen dengue to expose the semiconductor substrate by sequentially removing the nitride film from the nitride film on the upper portion of the semiconductor substrate, which is to be a device isolation region, from the semiconductor substrate. Forming a bond film pattern; forming a trench having a predetermined depth in the semiconductor substrates on both sides of the nitride film pattern; and forming a device isolation oxide film by thermally oxidizing the semiconductor substrate. Manufacturing Method 제1항에 있어서, 상기 질소 뎅글링 본드막을 5~100Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 산화막의 제조방법The method of claim 1, wherein the nitrogen dangling bond film is formed to a thickness of about 5 to about 100 μs. 제1항에 있어서, 상기 질소 뎅글링 본드막 형성 공정은 H2＋O2분위기에서 N2O 가스 또는 NH3가스를 첨가하여 형성하는 것을 특징으로 하는 반도체소자의 소자분리 산화막의 제조방법The method of claim 1, wherein the nitrogen dangling bond film forming process is performed by adding N 2 O gas or NH 3 gas in an H 2 + O 2 atmosphere. 제1항에 있어서, 상기 질소 뎅글링 본드막 형성공정을 800~1000℃온도에서 형성하는 것을 특징으로 하는 반도체소자의 소자분리 산화막의 제조방법2. The method of claim 1, wherein the nitrogen dangling bond film forming process is performed at a temperature of 800 ° C. to 1000 ° C. 3. 제1항에 있어서, 상기 패드산화막을 100~300Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 산화막의 제조방법The method of claim 1, wherein the pad oxide film is formed to a thickness of 100 to 300 Å. 제1항에 있어서, 상기 다결정실리콘층을 300~800Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 산화막의 제조방법The method of claim 1, wherein the polysilicon layer is formed to a thickness of 300 to 800 Å. 제1항에 있어서, 상기 질화막을 1000~3000Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 소자분리 산화막의 제조방법2. The method of claim 1, wherein the nitride film is formed to a thickness of 1000 to 3000 GPa. 제1항에 있어서, 상기 트랜치를 100~700Å깊이로 형성하는 것을 특징으로 하는 반도체 소자의 소자분리 산화막 제조방법The method of claim 1, wherein the trench is formed to a depth of 100 to 700 Å. 제1항에 있어서, 상기 트랜치를 별도의 질화막 패턴으로 메우고 열산화 공정을 실시하는 것을 특징으로 하는 반도체 소자의 소자분리 산화막 제조방법The method of claim 1, wherein the trench is filled with a separate nitride film pattern, and a thermal oxidation process is performed. 제1항에 있어서, 상기 소자분리 산화막 형성을 위한 열산화 공정을 900~1200℃온도에서 실시하는 것을 특징으로 하는 반도체 소자의 소자분리 산화막 제조방법The method of claim 1, wherein the thermal oxidation process for forming the device isolation oxide film is performed at a temperature of 900 to 1200 ° C. 3. 제1항에 있어서, 상기 소자분리 산화막 형성을 위한 열산화 공정을 건식이나 습식으로 실시하는 것을 특징으로 하는 반도체 소자의 소자분리 산화막 제조방법The method of claim 1, wherein the thermal oxidation process for forming the device isolation oxide film is performed in a dry or wet manner. 반도체기판상에 질소 뎅글링 본드막을 형성하는 공정과, 상기 질소 뎅글링 본드막상에 패드산화막을 형성하는 공정과, 상기 패드산화막상에 질화막을 형성하는 공정과, 상기 반도체기판에서 소자분리영역으로 예정되어 있는 부분 상측의 질화막에서 질소 뎅글링 본드막까지를 순차적으로 제거하여 반도체기판을 노출시키는 질화막과 패드산화막 및 질소 뎅글링 본드막 패턴을 형성하는 공정과, 상기 질화막 패턴 양측의 반도체기판에 예정된 깊이의 트랜치를 형성하는 공정과, 상기 반도체기판을 열산화시켜 소자분리 산화막을 형성하는 공정을 구비하는 반도체 소자의 소자분리 산화막의 제조방법Forming a nitrogen dangling bond film on the semiconductor substrate, forming a pad oxide film on the nitrogen dangling bond film, forming a nitride film on the pad oxide film, and forming a device isolation region in the semiconductor substrate. Forming a nitride film, a pad oxide film, and a nitrogen dangling bond film pattern exposing the semiconductor substrate by sequentially removing the nitrogen film from the nitride film on the upper portion of the portion; And forming a device isolation oxide film by thermally oxidizing the semiconductor substrate and forming a device isolation oxide film. 제12항에 있어서, 상기 트랜치를 별도의 질화막 패턴으로 메우고 열산화 공정을 실시하는 것을 특징으로 하는 반도체 소자의 소자분리 산화막 제조방법The method of claim 12, wherein the trench is filled with a separate nitride film pattern and a thermal oxidation process is performed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950003909A 1995-02-27 1995-02-27 Method for fabricating isolation oxide layer of semiconductor device KR100324813B1 (en)

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