KR960026612A - Method for manufacturing device isolation oxide film of semiconductor device - Google Patents

Method for manufacturing device isolation oxide film of semiconductor device Download PDF

Info

Publication number
KR960026612A
KR960026612A KR1019940040532A KR19940040532A KR960026612A KR 960026612 A KR960026612 A KR 960026612A KR 1019940040532 A KR1019940040532 A KR 1019940040532A KR 19940040532 A KR19940040532 A KR 19940040532A KR 960026612 A KR960026612 A KR 960026612A
Authority
KR
South Korea
Prior art keywords
oxide film
forming
nitride film
device isolation
film pattern
Prior art date
Application number
KR1019940040532A
Other languages
Korean (ko)
Other versions
KR100297170B1 (en
Inventor
엄금용
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940040532A priority Critical patent/KR100297170B1/en
Publication of KR960026612A publication Critical patent/KR960026612A/en
Application granted granted Critical
Publication of KR100297170B1 publication Critical patent/KR100297170B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체소자의 소자분리 산화막의 제조방법에 관한 것으로서, 반도체기판에서 소자분리 영역으로 예정되어 있는 부분을 노출시키는 중첩되어진 패드산화막과 다결정실리콘층 및 제1질화막 패턴을 형성하고, 상기 제1질화막 패턴 양측의 반도체기판에 깊이가 앝은 트랜치를 형성한 후, 상기 노출되어 있는 패드산화막 패턴 양측을 예정된 깊이로 등방성식각하여 홈을 형성하고 상기 홈과 트랜치를 제2질화막 패턴으로 메운 다음 노출되어 있는 반도체기판을 열산화시켜 소자분리 산화막을 형성하였으므로, 상기 홈을 메운 제2질화막 패턴에 의해 산소 에너지가 상하 양측으로 분산되어 확산되는 정도가 감소되므로 버즈빅의 크기가 감소되어 소자의 고집적화에 유리하고, 상기 트랜치 상부의 제2질화막 패턴에 의해 단차의 증가가 억제되어 원만한 토폴로지의 변화를 얻을 수 있어 후속 공정수율이 증가된다.The present invention relates to a method for manufacturing a device isolation oxide film of a semiconductor device, comprising: forming an overlapped pad oxide film, a polysilicon layer, and a first nitride film pattern exposing a portion of a semiconductor substrate, which is intended as a device isolation region, and forming a first nitride film pattern; After forming trenches having deep depths in the semiconductor substrates on both sides of the nitride film pattern, grooves are formed by isotropically etching both exposed pad oxide film patterns to a predetermined depth, and the grooves and trenches are filled with a second nitride film pattern and then exposed. Since the semiconductor substrate is thermally oxidized to form a device isolation oxide film, the degree of oxygen energy is dispersed and diffused up and down by the second nitride film pattern filled with the grooves is reduced, thereby reducing the size of the Buzzvik, which is advantageous for high integration of the device. The increase in the step is suppressed by the second nitride film pattern on the trench. The subsequent process is increased yield can be obtained, a change in the topology.

Description

반도체소자의 소자분리 산화막의 제조방법Method for manufacturing device isolation oxide film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 및 제1B도는 종래 기술에 따른 반도체소자의 소자분리 산화막의 제조 공정도.1A and 1B are manufacturing process diagrams of a device isolation oxide film of a semiconductor device according to the prior art.

Claims (7)

반도체기판상에 패드산화막을 형성하는 공정과, 상기 패드산화막상에 다결정실리콘층을 형성하는 공정과, 상기 다결정실리콘층 상에 제1질화막을 형성하는 공정과, 상기 반도체기판에서 소자분리영역으로 예정되어 있는 부분 상측의 제1질화막에서 패드산화막까지를 순차적으로 제거하여 반도체기판을 노출시키는 제1질화막과 다결정 실리콘층 및 패드산화막 패턴을 형성하는 공정과, 상기 패드산화막 패턴을 노출되어 있는 양측을 예정된 깊이로 등방성식각하여 홈을 형성하되 상기 홈의 상하측벽에 자연산화막을 형성하는 공정과, 상기 홈을 제2질화막 패턴으로 메우는 공정과, 상기 제1질화막 패턴에 의해 노출되어 있는 반도체기판을 열산화시켜 소자분리 산화막을 형성하는 공정을 구비하는 반도체소자의 소자분리 산화막의 제조방법.Forming a pad oxide film on the semiconductor substrate, forming a polysilicon layer on the pad oxide film, forming a first nitride film on the polysilicon layer, and forming a device isolation region in the semiconductor substrate. Forming a first nitride film, a polycrystalline silicon layer, and a pad oxide film pattern sequentially exposing the semiconductor substrate to the pad oxide film by sequentially removing the first nitride film on the upper portion of the portion; and preselecting both sides of the pad oxide film pattern. Forming a groove by isotropically etching to a depth, and forming a natural oxide film on the upper and lower side walls of the groove, filling the groove with a second nitride film pattern, and thermally oxidizing a semiconductor substrate exposed by the first nitride film pattern. Forming a device isolation oxide film to form a device isolation oxide film. 제1항에 있어서, 상기 패드산화막을 100~300Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 산화막의 제조방법.2. The method of claim 1, wherein the pad oxide film is formed to a thickness of 100 to 300 kHz. 제1항에 있어서, 상기 다결정실리콘층을 300~800Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분|리 산화막의 제조방법.The method of claim 1, wherein the polysilicon layer is formed to have a thickness of 300 to 800 占 퐉. 제1항에 있어서, 상기 제1질화막을 1000~3000Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자|분리 산화막의 제조방법.The method of claim 1, wherein the first nitride film is formed to a thickness of 1000 to 3000 Å. 제1항에 있어서, 상기 소자분리 산화막 형성을 위한 열산화 공정을 900~1200℃ 온도에서 실시하는 것을 특징|으로 하는 반도체소자의 소자분리 산화막의 제조방법.The method of claim 1, wherein the thermal oxidation process for forming the device isolation oxide film is performed at a temperature of 900 to 1200 ° C. 제1항에 있어서, 상기 소자분리 산화막 형성을 위한 열산화 공정을 건식이나 습식으로 실시하는 것을| 특징으로 하는 반도체소자의 소자분리 산화막의 제조방법.The method of claim 1, wherein the thermal oxidation process for forming the device isolation oxide film is performed by dry or wet method. A method of manufacturing a device isolation oxide film of a semiconductor device. 반도체기판상에 패드산화막을 형성하는 공정과, 상기 패드산화막상에 다결정실리콘층을 형성하는 공정과, 상|기 다결정실리콘층 상에 제1질화막을 형성하는 공정과, 상기 반도체기판에서 소자분리영역으로 예정되어 있는| 부분 상측의 제1질화막에서 패드산화막까지를 순차적으로 제거하여 반도체기판을 노출시키는 제1질화막과 다|결정실리콘층 및 패드산화막 패턴을 형성하는 공정과, 상기 제1질화막 패턴 양측의 반도체기판에 트랜치를 형|성하는 공정과, 상기 패드산화막 패턴을 노출되어 있는 양측을 예정된 깊이로 등방성식각하여 홈을 형성하되| 상기 홈의 상하 측벽에 자연산화막을 형성하는 공정과, 상기 홈과 트랜치를 제2질화막 패턴으로 메우는 공정|과, 상기 제1질화막 패턴에 의해 노출되어 있는 반도체기판을 열산화시켜 소자분리 산화막을 형성하는 공정을| 구비하는 반도체소자의 소자분리 산화막의 제조방법.Forming a pad oxide film on the semiconductor substrate, forming a polysilicon layer on the pad oxide film, forming a first nitride film on the phase polycrystalline silicon layer, and an isolation region in the semiconductor substrate Intended as | Forming a poly | silicon layer and a pad oxide film pattern, the first nitride film exposing the semiconductor substrate by sequentially removing the first nitride film from the upper portion of the portion and the pad oxide film; and trenches in the semiconductor substrates on both sides of the first nitride film pattern. Forming a groove by isotropically etching both sides of the pad oxide film pattern to a predetermined depth, and forming a groove | Forming a native oxide film on the upper and lower sidewalls of the groove, filling the groove and trench with a second nitride film pattern, and thermally oxidizing a semiconductor substrate exposed by the first nitride film pattern to form a device isolation oxide film. Process to make | A method of manufacturing a device isolation oxide film of a semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040532A 1994-12-31 1994-12-31 Method for fabricating isolating oxide layer of semiconductor device KR100297170B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040532A KR100297170B1 (en) 1994-12-31 1994-12-31 Method for fabricating isolating oxide layer of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040532A KR100297170B1 (en) 1994-12-31 1994-12-31 Method for fabricating isolating oxide layer of semiconductor device

Publications (2)

Publication Number Publication Date
KR960026612A true KR960026612A (en) 1996-07-22
KR100297170B1 KR100297170B1 (en) 2001-10-24

Family

ID=37528137

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940040532A KR100297170B1 (en) 1994-12-31 1994-12-31 Method for fabricating isolating oxide layer of semiconductor device

Country Status (1)

Country Link
KR (1) KR100297170B1 (en)

Also Published As

Publication number Publication date
KR100297170B1 (en) 2001-10-24

Similar Documents

Publication Publication Date Title
KR930020676A (en) Semiconductor memory device and manufacturing method thereof
KR960026612A (en) Method for manufacturing device isolation oxide film of semiconductor device
KR970053380A (en) Device Separation Method of Semiconductor Device
KR960026585A (en) Method for manufacturing device isolation oxide film of semiconductor device
KR960026603A (en) Method for manufacturing device isolation oxide film of semiconductor device
KR970003780A (en) Method of manufacturing device isolation oxide film of semiconductor device
KR970077497A (en) Method of forming device isolation film in semiconductor device
KR960005836A (en) Field oxide film formation method of a semiconductor device
KR930014896A (en) Manufacturing method of DRAM cell
KR960032676A (en) Method of manufacturing device isolation oxide film of semiconductor device
KR960026540A (en) Insulation Method of Semiconductor Devices
KR950021358A (en) Method for manufacturing field oxide film of semiconductor device
KR960026611A (en) Method for manufacturing device isolation oxide film of semiconductor device
KR980006088A (en) Method for fabricating device isolation film of semiconductor device
KR970018141A (en) Trench Etching Method of Silicon Substrate
KR960019574A (en) Method of forming dielectric film of semiconductor device
KR970003803A (en) Device Separator Manufacturing Method
KR970053416A (en) Device Separation Method of Semiconductor Device
KR970072180A (en) Method for forming field oxide film of semiconductor device
KR950021396A (en) Field oxide film manufacturing method
KR900015249A (en) Method for producing epipylom cell
KR970054000A (en) Formation method of capacitor electrode of semiconductor device
KR960005939A (en) Method of forming semiconductor device isolation film
KR970054006A (en) Manufacturing method of semiconductor device
KR960026620A (en) Semiconductor Device Separation Method Using Voids

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050422

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee