KR960028168A - Vertical Synchronous Signal Separation Circuit in Compound Synchronous Signal - Google Patents

Vertical Synchronous Signal Separation Circuit in Compound Synchronous Signal Download PDF

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Publication number
KR960028168A
KR960028168A KR1019940035990A KR19940035990A KR960028168A KR 960028168 A KR960028168 A KR 960028168A KR 1019940035990 A KR1019940035990 A KR 1019940035990A KR 19940035990 A KR19940035990 A KR 19940035990A KR 960028168 A KR960028168 A KR 960028168A
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South Korea
Prior art keywords
signal
synchronous signal
composite
vertical
field
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KR1019940035990A
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Korean (ko)
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KR0136468B1 (en
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박진호
김종선
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구자홍
엘지전자 주식회사
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Priority to KR1019940035990A priority Critical patent/KR0136468B1/en
Publication of KR960028168A publication Critical patent/KR960028168A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

본 발명은 복합 동기 신호에서 수직 동기 신호 분리회로에 관한 것으로 특히 수직 동기신호가 검출된 후 일정시간 동안 검출회로의 기능을 정지시켜 이 시간 동안 들어오는 잡음성분을 완전하게 차단할 수 있도록 한 것이다.The present invention relates to a vertical synchronizing signal separation circuit in a composite synchronizing signal, and in particular, to stop the function of the detection circuit for a predetermined time after the vertical synchronizing signal is detected so that the incoming noise component can be completely blocked during this time.

특징적인 구성으로는 복합동기신호가 수직동기신호 부분에서 대부분이 논리 '0'상태가 되는 것을 이용하여 수평동기신호의 반주기로 상기 복합동기신호를 체크하여 논리'0'인 상태가 일정 이상 계속되면 이를 필드의 시작임을 인지하여 필드시작신호를 발생시키는 필드시작신호검출부와, 상기 필드시작신호에 의해 수직동기신호를 발생시키는 수직동기신호발생부로 구성함에 있다.As a characteristic configuration, when the composite synchronous signal is a logic '0' state in the vertical synchronous signal portion, the composite synchronous signal is checked at half cycle of the horizontal synchronous signal, and the logic `` 0 '' is maintained for a predetermined time or more. A field start signal detection unit for generating a field start signal by recognizing the start of a field, and a vertical synchronization signal generation unit for generating a vertical synchronization signal by the field start signal.

Description

복합동기신호에서 수직동기신호분리회로Vertical Synchronous Signal Separation Circuit in Compound Synchronous Signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 수직동기신호분리회로의 블럭도. 제4도는 제3도의 필드시작신호검출부의 상세회로도, 제5도는 제3도의 필드시작신호검출부의 동작을 순서도형식으로 표현한 흐름도.3 is a block diagram of a vertical synchronous signal separation circuit according to the present invention. FIG. 4 is a detailed circuit diagram of the field start signal detection unit of FIG. 3, and FIG. 5 is a flowchart showing the operation of the field start signal detection unit of FIG.

Claims (4)

복합동기신호가 수직동기신호 부분에서 대부분이 논리'0'상태가 되는 것을 이용하여 수평동기신호보다 작은 주기로 상기 복합동기신호를 체크하여 논리'0'인 상태가 일정 횟수 이상 계속되면 이를 필드의 시작임을 인지하여 필드시작신호를 발생시키는 필드시작신호검출부와, 상기 필드시작신호에 의해 수직동기신호를 발생시키는 수직동기신호발생부로 구성함을 특징으로 하는 복합동기신호에서 수직동기신호분리회로.When the composite synchronous signal is a logic '0' state of the vertical synchronous signal portion, the composite synchronous signal is checked at a period smaller than the horizontal synchronous signal, and when the state of logic '0' continues for a predetermined number of times, it starts the field. And a field start signal detecting unit for generating a field start signal by recognizing that the signal is generated and a vertical synchronizing signal generating unit generating a vertical synchronizing signal by the field start signal. 제1항에 있어서, 상기 필드시작신호검출부는 외부 동기신호를 읽어 들이는 시점을 지정하기 위해 복합동기신호의 수평동기성분과 하강에지에서 위상을 일치시킨 수평동기신호의 반주기 50%듀티비의 구형파를 만들고 이의 상승에지에서 외부도익신호의 상태를 읽어들이는 것을 특징으로 하는 복합동기신호에서 수직도익신호분리회로.The square wave of the half period 50% duty ratio of the horizontal synchronous signal of which the phase is matched at the falling edge and the horizontal synchronous component of the complex synchronous signal to designate the point of time when the external start signal is read. And a vertical gain signal separation circuit of the composite synchronous signal, characterized in that for reading the state of the external wing signal at its rising edge. 제1항에 있어서, 상기 필드시작 신호검출부는 복합동기신호와 위상이 일치하는 수평동기신호와 같은 주기의 50%듀티비의 구형파의 상태를 읽어들이고 상기의 동작을 일정 횟수이상 반복한 후 그 결과가 처음에 설정한 값과 일치하면 이를 필드의 시작으로 인지하여 필드시작신호를 발생시키는 것을 특징으로하는 복합동기신호에서 수직동기신호분리회로.The method of claim 1, wherein the field start signal detection unit reads a state of a square wave having a duty cycle of 50% duty ratio in the same period as a horizontal synchronization signal in phase with the composite synchronization signal, and repeats the above operation a predetermined number of times. The vertical synchronous signal separation circuit of the composite synchronous signal according to claim 1, wherein when the value coincides with the value initially set, the start signal is recognized as the start of the field. 제1항에 있어서, 필드시작신호검출부는 반주기로 상기 복합동기신호를 체크함을 특징으로 하는 복합동기신호분리회로.2. The composite synchronous signal separation circuit according to claim 1, wherein the field start signal detection unit checks the composite synchronous signal at half cycles. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035990A 1994-12-22 1994-12-22 Circuit for separating vertical synchronization signals KR0136468B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940035990A KR0136468B1 (en) 1994-12-22 1994-12-22 Circuit for separating vertical synchronization signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940035990A KR0136468B1 (en) 1994-12-22 1994-12-22 Circuit for separating vertical synchronization signals

Publications (2)

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KR960028168A true KR960028168A (en) 1996-07-22
KR0136468B1 KR0136468B1 (en) 1998-11-16

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