KR960028168A - Vertical Synchronous Signal Separation Circuit in Compound Synchronous Signal - Google Patents
Vertical Synchronous Signal Separation Circuit in Compound Synchronous Signal Download PDFInfo
- Publication number
- KR960028168A KR960028168A KR1019940035990A KR19940035990A KR960028168A KR 960028168 A KR960028168 A KR 960028168A KR 1019940035990 A KR1019940035990 A KR 1019940035990A KR 19940035990 A KR19940035990 A KR 19940035990A KR 960028168 A KR960028168 A KR 960028168A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- synchronous signal
- composite
- vertical
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 19
- 238000000926 separation method Methods 0.000 title claims abstract description 6
- 150000001875 compounds Chemical class 0.000 title 1
- 238000001514 detection method Methods 0.000 claims abstract description 6
- 239000002131 composite material Substances 0.000 claims abstract 10
- 238000000034 method Methods 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Synchronizing For Television (AREA)
Abstract
본 발명은 복합 동기 신호에서 수직 동기 신호 분리회로에 관한 것으로 특히 수직 동기신호가 검출된 후 일정시간 동안 검출회로의 기능을 정지시켜 이 시간 동안 들어오는 잡음성분을 완전하게 차단할 수 있도록 한 것이다.The present invention relates to a vertical synchronizing signal separation circuit in a composite synchronizing signal, and in particular, to stop the function of the detection circuit for a predetermined time after the vertical synchronizing signal is detected so that the incoming noise component can be completely blocked during this time.
특징적인 구성으로는 복합동기신호가 수직동기신호 부분에서 대부분이 논리 '0'상태가 되는 것을 이용하여 수평동기신호의 반주기로 상기 복합동기신호를 체크하여 논리'0'인 상태가 일정 이상 계속되면 이를 필드의 시작임을 인지하여 필드시작신호를 발생시키는 필드시작신호검출부와, 상기 필드시작신호에 의해 수직동기신호를 발생시키는 수직동기신호발생부로 구성함에 있다.As a characteristic configuration, when the composite synchronous signal is a logic '0' state in the vertical synchronous signal portion, the composite synchronous signal is checked at half cycle of the horizontal synchronous signal, and the logic `` 0 '' is maintained for a predetermined time or more. A field start signal detection unit for generating a field start signal by recognizing the start of a field, and a vertical synchronization signal generation unit for generating a vertical synchronization signal by the field start signal.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명에 의한 수직동기신호분리회로의 블럭도. 제4도는 제3도의 필드시작신호검출부의 상세회로도, 제5도는 제3도의 필드시작신호검출부의 동작을 순서도형식으로 표현한 흐름도.3 is a block diagram of a vertical synchronous signal separation circuit according to the present invention. FIG. 4 is a detailed circuit diagram of the field start signal detection unit of FIG. 3, and FIG. 5 is a flowchart showing the operation of the field start signal detection unit of FIG.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940035990A KR0136468B1 (en) | 1994-12-22 | 1994-12-22 | Vertical Sync Signal Separation Circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940035990A KR0136468B1 (en) | 1994-12-22 | 1994-12-22 | Vertical Sync Signal Separation Circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960028168A true KR960028168A (en) | 1996-07-22 |
KR0136468B1 KR0136468B1 (en) | 1998-11-16 |
Family
ID=19402925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940035990A Expired - Lifetime KR0136468B1 (en) | 1994-12-22 | 1994-12-22 | Vertical Sync Signal Separation Circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0136468B1 (en) |
-
1994
- 1994-12-22 KR KR1019940035990A patent/KR0136468B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR0136468B1 (en) | 1998-11-16 |
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Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19941222 |
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Comment text: Notification of reason for refusal Patent event date: 19970919 Patent event code: PE09021S01D |
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Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19971229 |
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