KR960027673A - Clock Transmitter and Receiver - Google Patents

Abstract

The present invention relates to a clock transmitting and receiving device which transmits an alarm signal for notifying its own failure situation when the clock transmitting device transmits a clock to the clock receiving device.

According to the present invention, when the clock transmitting device transmits an alarm signal to the clock receiving device side, a plurality of alarm signals corresponding to a failure can be transmitted through a single line, so that the number of alarm signal transmission lines can be reduced and economical. Can improve.

Description

Clock Transmitter and Receiver

Since this is an open matter, no full text was included.

2 is a block diagram of a clock transmission and reception apparatus according to the present invention.

Claims (3)

In the clock transmitting and receiving apparatus, a clock transmitting apparatus (30) for transmitting a plurality of alarm signals corresponding to a fault condition generated in the clock transmitting apparatus through a single line, and a clock receiving apparatus from the clock transmitting and receiving apparatus (30). And a clock receiving device (40) for receiving a plurality of alarm signals received from the time clock transmitting device (30) through a single line. The clock transmitter / receiver 30 according to claim 1, wherein the clock transmitter / receiver 30 receives a clock from the clock generator 32 at the clock stage CLK and a high level power is applied to the clear stage CLR to count the output stages. A counter 33 for outputting a divided signal having a different period through Q1 to Q4, and a first AND gate for performing an AND operation on the signals applied from the output terminal Q1 and the output terminal Q2 of the counter 33. 35), a second AND gate 36 for performing an AND operation on the signal applied from the output terminal Q3 of the counter 33 and the signal applied from the first AND gate 35, and an output terminal of the counter 33. A third AND gate 37 for performing an AND operation on the signal applied from Q4 and the signal applied from the second AND gate 36, and an input terminal IN. A signal is received from the output terminal Q1 of the counter 33, a signal from the first AND gate 35 is applied to an input terminal IN1, and a signal is received from the second AND gate 36 at an input terminal IN2. Signal from the third AND gate 37 is applied to the input terminal IN3, and the input terminal IN according to the alarm control signal applied from the processor 31 to the control terminal C. And a multiplexer (34) for selecting one of the input signals from IN3) and transmitting the signal as an alarm signal to the clock receiving device (40) through a single line. The clock receiving apparatus 40 of claim 1, wherein the clock receiving apparatus 40 is applied through a single line from the first inverter 45 for inverting the clock applied from the clock transmitting apparatus 30 and the clock transmitting and receiving apparatus 30. The second inverter 46 which inverts the alarm signal and the clock terminal CLK receive the clock from the first inverter 45 and the clear terminal CLR receives the signal from the second inverter 46. The counter 44 which outputs binary information through each output terminal Q1 to Q4 by counting operation, and the binary information applied from the output terminals Q1 to Q4 of the counter 42 are received from the clock transmitting and receiving device 30. And a latch unit (43) for latching in accordance with a signal applied to a clock terminal (CLK) and outputting the signal to the processor (41) side through output terminals (Q1 to Q4). ※ Note: The disclosure is based on the initial application.