KR960027341A - Encoder pulse division circuit and method - Google Patents

Encoder pulse division circuit and method Download PDF

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Publication number
KR960027341A
KR960027341A KR1019940040658A KR19940040658A KR960027341A KR 960027341 A KR960027341 A KR 960027341A KR 1019940040658 A KR1019940040658 A KR 1019940040658A KR 19940040658 A KR19940040658 A KR 19940040658A KR 960027341 A KR960027341 A KR 960027341A
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South Korea
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signal
response
input signal
output signal
operation means
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KR1019940040658A
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Korean (ko)
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KR0165312B1 (en
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문용기
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김광호
삼성전자 주식회사
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Publication of KR0165312B1 publication Critical patent/KR0165312B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/54—Ring counters, i.e. feedback shift register counters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Transmission And Conversion Of Sensor Element Output (AREA)

Abstract

본 발명은 엔코더 펄스 분주회로 및 방법을 공개한다. 그 회로는 방향성신호에 응답하여 제1입력신호와 제1체배신호에 응답하여 궤환되는 상기 분주된 출력신호를 가감하여 출력하기 위한 제1연산수단과, 상기 제1연산수단의 출력신호와 제2입력신호를 비교하여 상기 제1연산수단의 출력신호가 상기 제2입력신호보다 크거나 같은 경우에 제1신호를 발생하고 상기 제1연산수단의 출력신호가 상기 제2입력신호보다 작은 경우에 제2신호를 발생하기 위한 판단수단, 상기 방향성 신호에 응답하고 상기 판단수단의 제1신호에 응답하여 상기 제1연산수단의 출력신호와 상기 제2입력신호를 입력하여 가감하기 위한 제2연산수단, 제2체배신호에 응답하여 상기 제2연산수단의 출력신호를 상기 제1연산수단으로 궤환하기 위한 궤환수단으로 구성되어 있다. 따라서, 제1입력신호를 제2입력신호로 나눈 분주비를 가진 엔코더 펄스를 발생할 수가 있다.The present invention discloses an encoder pulse division circuit and method. The circuit comprises first and second operating means for subtracting and outputting the divided output signal fed back in response to the first input signal and the first multiplier signal in response to the directional signal, and the output signal and the second output signal of the first operation means. Comparing an input signal to generate a first signal when the output signal of the first operation means is greater than or equal to the second input signal and the output signal of the first operation means is smaller than the second input signal Determination means for generating two signals, second operation means for inputting or subtracting an output signal of the first operation means and the second input signal in response to the directional signal and in response to the first signal of the determination means; And feedback means for returning the output signal of the second calculation means to the first calculation means in response to a second multiplication signal. Therefore, an encoder pulse having a division ratio obtained by dividing the first input signal by the second input signal can be generated.

Description

엔코더 펄스 분주회로 및 방법Encoder pulse division circuit and method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (2)

방향성신호에 응답하여 제1입력신호와 제1체배신호에 응답하여 궤환되는 상기 분주된 출력신호를 가감하여 출력하기 위한 제1연산수단의 출력신호와 제2입력신호를 비교하여 상기 제1연산수단의 출력신호가 상기 제2입력신호보다 크거나 같은 경우에 제1신호를 발생하고 상기 제1연산수단의 출력신호가 상기 제2입력신호보다 작은 경우에 제2신호를 발생하기 위한 판단수단; 상기 방향성 신호에 응답하고 상기 판다수단의 제1신호에 응답하여 상기 제1연산수단의 출력신호와 상기 제2입력신호를 입력하여 가감하기 위한 제2연산수단; 2체배신호에 응답하여 상기 제2연산수단의 출력신호를 제1연산수단으로 궤환하기 위한 궤환수단을 구비하는 것을 특징으로 하는 엔코더의 펄스를 제1입력신호를 제2입력신호로 분주하여 분주된 펄스를 발생하는 것을 특징으로 하는 엔코더 펄스 분주기.The first operation means by comparing the second input signal with the output signal of the first operation means for subtracting and outputting the divided output signal fed back in response to the first input signal and the first multiplier signal in response to the directional signal; Judging means for generating a first signal when the output signal of the signal is greater than or equal to the second input signal and generating a second signal when the output signal of the first calculation means is smaller than the second input signal; Second calculating means for inputting and subtracting the output signal of the first calculating means and the second input signal in response to the directional signal and in response to the first signal of the panda means; And a feedback means for returning the output signal of the second operation means to the first operation means in response to the double multiplication signal. The pulses of the encoder are divided by dividing the first input signal into the second input signal. An encoder pulse divider, characterized in that to generate a pulse. 방향성신호에 응답하여 제1입력신호와 제1체배신호에 응답하여 궤환되는 상기 분주된 출력신호를 가감하는 단계; 상기 제1연산수단의 출력신호와 제2입력신호를 비교하여 상기 제1연산수단의 출력신호가 상기 제2입력신호보다 크거나 같은 경우에 제1신호를 발생하고 상기 제1연산수단의 출력신호가 상기 제2입력신호보다 작은 경우에 제2신호를 발생하는 단계; 상기 방향성 신호에 응답하고 상기 판단수단의 제1신호에 응답하여 상기 제1연산수단의 출력신호와 상기 제2입력신호를 입력하여 가감하는 단계; 2체배신호에 응답하여 상기 제2연산수단의 출력신호를 상기 제1연산수단으로 출력하는 단계를 구비한 것을 특징으로 하는 엔코더의 펄스를 제1입력신호를 제2입력신호로 분주하여 분주된 펄스를 발생하는 것을 특징으로 하는 엔코더 펄스 분주방법.Subtracting the divided output signal fed back in response to a first input signal and a first multiplied signal in response to a directional signal; Comparing the output signal of the first operation means and the second input signal, when the output signal of the first operation means is greater than or equal to the second input signal, a first signal is generated and the output signal of the first operation means. Generating a second signal when is less than the second input signal; Inputting or subtracting an output signal of the first calculating means and the second input signal in response to the directional signal and in response to the first signal of the determining means; And outputting the output signal of the second operation means to the first operation means in response to the multiplication signal. The pulses are divided by dividing the pulse of the encoder into the second input signal. Encoder pulse dispensing method characterized in that for generating. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040658A 1994-12-31 1994-12-31 Encoder pulse divider circuit and its method KR0165312B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040658A KR0165312B1 (en) 1994-12-31 1994-12-31 Encoder pulse divider circuit and its method

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Application Number Priority Date Filing Date Title
KR1019940040658A KR0165312B1 (en) 1994-12-31 1994-12-31 Encoder pulse divider circuit and its method

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KR960027341A true KR960027341A (en) 1996-07-22
KR0165312B1 KR0165312B1 (en) 1999-03-20

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