KR960026484A - Wafer Forming Method - Google Patents

Wafer Forming Method Download PDF

Info

Publication number
KR960026484A
KR960026484A KR1019940037787A KR19940037787A KR960026484A KR 960026484 A KR960026484 A KR 960026484A KR 1019940037787 A KR1019940037787 A KR 1019940037787A KR 19940037787 A KR19940037787 A KR 19940037787A KR 960026484 A KR960026484 A KR 960026484A
Authority
KR
South Korea
Prior art keywords
wafer
epitaxial
high temperature
temperature annealing
sio
Prior art date
Application number
KR1019940037787A
Other languages
Korean (ko)
Other versions
KR0162137B1 (en
Inventor
허상범
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940037787A priority Critical patent/KR0162137B1/en
Publication of KR960026484A publication Critical patent/KR960026484A/en
Application granted granted Critical
Publication of KR0162137B1 publication Critical patent/KR0162137B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

본 발명은 반도체 장치의 제조에 사용되는 실리콘 웨이퍼의 어닐링방법에 관한 것으로, 웨이퍼 위에 에피택셜 성장법으로 에피택셜막을 증착시키는 웨이퍼의 제조방법에 있어서, 에피택셜 증착공정후 웨이퍼의 초기 산화 공정단계 이전에 고온어닐링공정이 추가로 포함하는 것을 특징으로 함으로써, 에피택셜 막에 발생한 결정결함이 고온 어닐링공정에 의하여, 점결함의 농도 감소로 인하여 Si-SiO2계면 특성을 향상되고, 실리콘 웨이퍼내의 산소 함량을 제어를 통하여 적층 결함의 발생을 배제할 수 있다. 따라서, SiO2의 항복 특성을 향상시켜 반도체 장치의 품질을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an annealing method of a silicon wafer used in the manufacture of a semiconductor device, the method for manufacturing a wafer in which an epitaxial film is deposited on the wafer by an epitaxial growth method, before the initial oxidation process step of the wafer after the epitaxial deposition process. By further comprising a high temperature annealing process, the crystal defects generated in the epitaxial film is improved by the high temperature annealing process to improve the Si-SiO 2 interface characteristics due to the decrease in the concentration of the point defects, and to increase the oxygen content in the silicon wafer. Control can eliminate the occurrence of stacking defects. Therefore, the yield characteristics of SiO 2 can be improved to improve the quality of the semiconductor device.

Description

웨이퍼 형성방법Wafer Forming Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (4)

웨이퍼 위에 에피택셜 성장법으로 에피택셜막을 성장시키는 웨이퍼 제조방법에 있어서, 에피택셜 증착공정 후 웨이퍼의 초기 산화 공정단계 이전에 고온 어닐링공정이 추가로 포함하는 것을 특징으로 하는 웨이퍼 제조 방법.A wafer manufacturing method for growing an epitaxial film on the wafer by epitaxial growth, wherein the high temperature annealing process is further included after the epitaxial deposition process and before the initial oxidation process of the wafer. 제1항에 있어서, 상기 에피택셜 증착전의 웨이퍼는 쵸크랄스키 결정성장법에 의하여 성장된 웨이퍼인 것을 특징으로 하는 웨이퍼 제조 방법.The wafer manufacturing method according to claim 1, wherein the wafer before epitaxial deposition is a wafer grown by Czochralski crystal growth method. 제2항에 있어서, 상기 고온 어닐링 공정은 실리콘 기판상에 에피택셜 성장시킨 후의 경우에, 1000∼1200℃, 불활성 기체 상태에서 행해지는 것을 특징으로 하는 웨이퍼 제조 방법.The wafer fabrication method according to claim 2, wherein the high temperature annealing step is performed in an inert gas state at 1000 to 1200 占 폚 after epitaxial growth on a silicon substrate. 제3항에 있어서, 상기 불활성 기체는 수소, 질소, 또는 아르곤인 것을 특징으로 하는 웨이퍼 제조 방법.The method of claim 3, wherein the inert gas is hydrogen, nitrogen, or argon. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940037787A 1994-12-28 1994-12-28 Formation method of wafer KR0162137B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940037787A KR0162137B1 (en) 1994-12-28 1994-12-28 Formation method of wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940037787A KR0162137B1 (en) 1994-12-28 1994-12-28 Formation method of wafer

Publications (2)

Publication Number Publication Date
KR960026484A true KR960026484A (en) 1996-07-22
KR0162137B1 KR0162137B1 (en) 1999-02-01

Family

ID=19404173

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940037787A KR0162137B1 (en) 1994-12-28 1994-12-28 Formation method of wafer

Country Status (1)

Country Link
KR (1) KR0162137B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100323061B1 (en) * 1999-08-24 2002-02-07 이 창 세 Method of grown-in defects reduction on the surface and near surface of silicon wafer
KR100347141B1 (en) * 2000-01-05 2002-08-03 주식회사 하이닉스반도체 Manufacturing method for a epitaxial silicon wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100323061B1 (en) * 1999-08-24 2002-02-07 이 창 세 Method of grown-in defects reduction on the surface and near surface of silicon wafer
KR100347141B1 (en) * 2000-01-05 2002-08-03 주식회사 하이닉스반도체 Manufacturing method for a epitaxial silicon wafer

Also Published As

Publication number Publication date
KR0162137B1 (en) 1999-02-01

Similar Documents

Publication Publication Date Title
US5037774A (en) Process for the production of semiconductor devices utilizing multi-step deposition and recrystallization of amorphous silicon
EP0257917A3 (en) Method of producing soi devices
US6436846B1 (en) Combined preanneal/oxidation step using rapid thermal processing
US5686350A (en) Method for fabricating defect-free compound semiconductor thin film on dielectric thin film
KR960026484A (en) Wafer Forming Method
JPH10144698A (en) Silicon wafer and its manufacture
US5173127A (en) Semi-insulating inp single crystals, semiconductor devices having substrates of the crystals and processes for producing the same
JPH01134912A (en) Manufacture of semiconductor thin film
JPH0529234A (en) Epitaxial crowing method
KR960004902B1 (en) Preparation of polycrystalline silicon thin film
JPH06333822A (en) Semiconductor device
JP2588632B2 (en) Oxygen precipitation method for silicon single crystal
JP2853226B2 (en) Semiconductor device and manufacturing method thereof
JPS6197819A (en) Method for vapor growth
JPH02103924A (en) Manufacture of semiconductor device
JPH03270236A (en) Manufacture of semiconductor device
JPH04151820A (en) Semiconductor device
KR0167239B1 (en) Method of isolation film on a semiconductor device
JPH01179788A (en) Method for growing iii-v compound semiconductor on si substrate
KR100500394B1 (en) Manufacturing method of Epitaxial silicon wafer
JPS61131434A (en) Manufacture of semiconductor device
JPH05283350A (en) Manufacture of epitaxial semiconductor wafer
JPS63239935A (en) Selective growing method for silicon
JPH05198505A (en) Formation of tft polysilicon thin film
JPH0425135A (en) Semiconductor substrate

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090727

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee