KR960026138A - Method for manufacturing contact and via plug using silicide - Google Patents

Method for manufacturing contact and via plug using silicide Download PDF

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Publication number
KR960026138A
KR960026138A KR1019940032827A KR19940032827A KR960026138A KR 960026138 A KR960026138 A KR 960026138A KR 1019940032827 A KR1019940032827 A KR 1019940032827A KR 19940032827 A KR19940032827 A KR 19940032827A KR 960026138 A KR960026138 A KR 960026138A
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KR
South Korea
Prior art keywords
thin film
silicide
metal
depositing
plug
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Application number
KR1019940032827A
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Korean (ko)
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KR0160545B1 (en
Inventor
이진호
Original Assignee
양숭택
재단법인 한국전자통신연구소
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Priority to KR1019940032827A priority Critical patent/KR0160545B1/en
Publication of KR960026138A publication Critical patent/KR960026138A/en
Application granted granted Critical
Publication of KR0160545B1 publication Critical patent/KR0160545B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

본 발명에 따른 컨택구조는 기존의 방법과 같이 컨택 개구(contact opening)를 형성한 후, 스텝 커브리지(step coverage)가 우수한 폴리실리콘(또는, 비정질 실리콘)을 증착하고 되식각한 후, 폴리실리콘(또는, 비정질 실리콘) 플러그를 만든다.In the contact structure according to the present invention, after forming a contact opening as in the conventional method, after depositing and re-etching polysilicon (or amorphous silicon) having excellent step coverage, the polysilicon (Or amorphous silicon) to make a plug.

그 위에 Pt, Ti, Co나, Ni 등을 증착한 다음, 열처리(annealing)한 후, 반응되지 않은 Pt, Ti, Co나, Ni등에 대한 습식화학식각(wet chemicl etch)을 수행하여 선택적으로 실리사이드가 형성되도록 한다.Pt, Ti, Co or Ni is deposited thereon, followed by annealing, followed by wet chemicl etching of unreacted Pt, Ti, Co or Ni to selectively suicide. To be formed.

이러한 공정은 기존의 컨택공정에다 몇 가지의 간단한 공정들을 추가하는 것에 의해 구현되며, 이러한 실리사이드를 이용한 플러그의 형성방법은 스텝 커버리지가 우수할 뿐만 아니라, 저저항값이 기재되며, 초 서브마이코론(deep sub-micron)급 이하의 소자의 컨택 및 비어 공정에 적합한 기술이다.This process is implemented by adding a few simple processes to the existing contact process, the method of forming the plug using the silicide not only has a good step coverage, but also describes a low resistance value, ultra-submicron ( This technology is suitable for the contact and via process of deep sub-micron) devices and below.

Description

실리사이드를 이용한 컨택 및 비어 플러그의 제조방법Method for manufacturing contact and via plug using silicide

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 (가) 내지 (파)는 본 발명의 제조방법을 공정순서대로 나타낸 단면도.2 is a cross-sectional view (a) to (wave) showing the manufacturing method of the present invention in the order of process.

Claims (2)

반도체 장치의 제조방법에 있어서, 기판(1) 상에 분리영역(2)을 형성하고 집적회로 소자를 형성한 후 층간절연막용 산화막(6)을 증착하는 단계와; 상기 산화막(6) 위에 포토레지스트를 도포하여 컨택 패턴을 정의한 후 상기 산화막(6)을 식각하고 상기 포토레지스트를 제거하여 컨택(7)을 형성하는 단계와; 실리사이드의 생성을 위해 금속 박막(8)을 약 10~100nm정도의 두께로 증착하는 단계와; 상기 금속 박막(8) 위에 폴리실리콘 박막(또는, 비정질 실리콘 박막) (9)을 상온~500℃의 온도에서 증착하고 도핑시키는 단계와; 되식각 방법으로, 상기 폴리실리콘 박막(또는 비정질 실리콘 박막)(9) 중 플러그(10) 부분만 남기고 나머지 부분을 제거하는 단계와; 실리사이드의 생성을 위해, 금속 박막(11)을 10~100nm의 두께로 증착하고, 300℃~700℃의 온도에서 열처리하여 실리사이드 플러그(12)를 형성한 후, 실리사이드가 되지 않은 금속 박막을 제거하는 단계와; 배선용 금속(13)을 증착하고, 원하는 패턴대로 식각하여 금속 배선을 형성하는 단계와; 금속 배선 위에 층간절연막(14)을 형성한 후 식각하여 비어 호울(15)을 형성하고, 금속 박막(16)을 10~100nm의 두께로 증착하는 단계와; 폴리실리콘 박막(또는, 비정질 실리콘 박막)을 상온~500℃의 온도에서 증착한 후, 플러그(17)만 남기고 나머지를 제거하는 단계와; 실리사이드의 생성을 위한 금속 박막(18)을 10~100nm의 두께로 증착하고, 300℃~700℃의 온도에서 열처리하여 실리사이드 플러그(19)를 형성한 후, 실리사이드가 되지 않은 금속 박막을 제거한 다음, 배선용 금속(20)을 증착하고 원하는 패턴으로 식각하여 금속배선을 형성하는 단계를; 포함하는 것을 특징으로 하는 실리사이드를 이용한 컨택 및 비어 플러그의 제조방법.A method of manufacturing a semiconductor device, comprising: forming an isolation region (2) on a substrate (1), forming an integrated circuit device, and then depositing an oxide film (6) for an interlayer insulating film; Applying a photoresist on the oxide film (6) to define a contact pattern, and then etching the oxide film (6) and removing the photoresist to form a contact (7); Depositing a metal thin film 8 to a thickness of about 10 to 100 nm to produce silicide; Depositing and doping a polysilicon thin film (or an amorphous silicon thin film) 9 on the metal thin film 8 at a temperature of room temperature to 500 ° C .; Removing the remaining portion of the polysilicon thin film (or amorphous silicon thin film) 9 by leaving only the plug 10 portion; In order to form the silicide, the metal thin film 11 is deposited to a thickness of 10 to 100 nm, heat treated at a temperature of 300 ° C. to 700 ° C. to form the silicide plug 12, and then the metal silicide which is not silicide is removed. Steps; Depositing a wiring metal 13 and etching the desired pattern to form a metal wiring; Forming an via hole 15 by forming an interlayer insulating film 14 on the metal wiring, and then etching the metal thin film 16 to a thickness of 10 to 100 nm; Depositing a polysilicon thin film (or amorphous silicon thin film) at a temperature of room temperature to 500 ° C., leaving only the plug 17 and removing the remainder; After depositing the metal thin film 18 for the production of silicide to a thickness of 10 ~ 100nm, and heat treatment at a temperature of 300 ℃ ~ 700 ℃ to form a silicide plug 19, after removing the non-silicide metal thin film, Depositing the wiring metal 20 and etching the desired pattern to form a metal wiring; Method for producing a contact and the via plug using a silicide, characterized in that it comprises a. 제1항에 있어서, 상기 금속 박막(8,11,16)은 적어도 Pt, Co, Ti, Ni 중 하나로 형성되는 것을 특징으로 하는 실리사이드를 이용한 컨택 및 비어 플러그의 제조방법.The method of claim 1, wherein the metal thin film (8, 11, 16) is formed of at least one of Pt, Co, Ti, and Ni. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940032827A 1994-12-05 1994-12-05 Fabrication method of contact and via plug silicide KR0160545B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940032827A KR0160545B1 (en) 1994-12-05 1994-12-05 Fabrication method of contact and via plug silicide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940032827A KR0160545B1 (en) 1994-12-05 1994-12-05 Fabrication method of contact and via plug silicide

Publications (2)

Publication Number Publication Date
KR960026138A true KR960026138A (en) 1996-07-22
KR0160545B1 KR0160545B1 (en) 1999-02-01

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KR100851438B1 (en) * 2007-02-05 2008-08-11 주식회사 테라세미콘 Method for fabricating semiconductor device

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