KR960025758A - Sense Amplifier Circuit - Google Patents

Sense Amplifier Circuit Download PDF

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Publication number
KR960025758A
KR960025758A KR1019940038071A KR19940038071A KR960025758A KR 960025758 A KR960025758 A KR 960025758A KR 1019940038071 A KR1019940038071 A KR 1019940038071A KR 19940038071 A KR19940038071 A KR 19940038071A KR 960025758 A KR960025758 A KR 960025758A
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KR
South Korea
Prior art keywords
sense amplifier
pair
bit lines
barrier
voltage
Prior art date
Application number
KR1019940038071A
Other languages
Korean (ko)
Other versions
KR0143028B1 (en
Inventor
황문찬
황홍선
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019940038071A priority Critical patent/KR0143028B1/en
Priority to TW084111313A priority patent/TW278241B/en
Priority to JP7315391A priority patent/JPH08235863A/en
Publication of KR960025758A publication Critical patent/KR960025758A/en
Application granted granted Critical
Publication of KR0143028B1 publication Critical patent/KR0143028B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 데이타비트를 감지증폭하는 센스앰프회로에 관한 것이다.The present invention relates to a sense amplifier circuit for sensing and amplifying data bits.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래에는 배리어 트랜지통과한 전압을 엔형센스앰프의 제어전압으로 사용하다보니 낮은 전원전압상태에서 오동작이 빈번히 발생하였다. 본 발명에서는 센스앰프에서 발생하는 오동작을 방지하면서 고속을 감지동작을 수행하는 센스앰프를 구현하고자 한다.Conventionally, since the voltage passed through the barrier transition is used as the control voltage of the N-type sense amplifier, malfunction occurs frequently at a low power supply voltage. The present invention is to implement a sense amplifier for performing a high-speed sensing operation while preventing a malfunction occurring in the sense amplifier.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

배리어 트랜지스터를 통과하기전의 비트라인쌍에 인가된 높은 전압을 엔형센스앰프의 제어전압으로 사용하므로서 오동작이 방지되면서 고속으로 정확하게 감지증폭동작을 수행하는 센스앰프가 구현된다.By using a high voltage applied to the pair of bit lines before passing through the barrier transistor as a control voltage of the N-type sense amplifier, a sense amplifier is implemented to perform a sense amplifier operation at high speed and accurately while preventing malfunction.

4. 발명의 중요한 용도4. Important uses of the invention

낮은 전원전압에서 오동작이 줄어들고 고속으로 정확하게 감지증폭동작을 수행하는 센스앰프가 제공되므로서, 고속동작하는 고집적 다이나믹 랜덤 액세스 메모리의 전반적인 신뢰성을 높이게 된다.A sense amplifier is provided that reduces malfunctions at low supply voltages and performs accurate sense amplification at high speeds, thereby increasing the overall reliability of high-speed, highly integrated dynamic random access memories.

Description

센스앰프회로Sense Amplifier Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 센스앰프를 보여주는 회로도, 제3도는 제2도의 리드동작 타이밍도.2 is a circuit diagram showing a sense amplifier according to the present invention, and FIG. 3 is a read operation timing diagram of FIG.

Claims (2)

다수의 비트라인쌍과 다수의 워드라인을 가지며 각 한쌍의 비트라인은 배리어 트랜지스터로 분할되고 상기배리어 트랜지스터로 분할된 각 한쌍의 비트라인의 일측에서 상기 다수의 워드라인과의 상기 각 비트라인과 교차점에 다수의 메모리셀들을 가지며 상기 일측의 각 한쌍의 비트라인의 사이에 접속된 피형센스앰프와 상기 일측과 반대되는 타측의 각 한쌍의 비트라인사이에 접속된 엔형센스앰프와 상기 일측의 각 한쌍의 비트라인사이에 접속된 등화회로를 가지는다이나믹 랜덤 액세스 메모리에 있어서, 상기 엔형센스앰프를 구성하는 한쌍의 엔채널 트랜지스터의 채널이 직렬접속도어상기 타측에 있는 상기 각 한쌍의 비트라인사이에 접속되고 상기 한쌍의 엔채널 트랜지스터의 각 게이트는 상기 일측의각 한쌍의 비트라인과 교차접속되어 있고 상기 한쌍의 엔채널 트랜지스터의 직렬접속공통점은 상기 엔형센스앰프를 활성화하기위한 활성화 트랜지스터와 접속되어 있음을 특징으로 하는 다이나믹 랜덤 액세스 메모리의 엔형센스앰프A pair of bit lines having a plurality of bit line pairs and a plurality of word lines, each pair of bit lines being divided into barrier transistors and crossing each said bit line with said plurality of word lines at one side of each pair of bit lines divided by said barrier transistor A pair of n-type sense amplifiers connected to each other between the pair of type sense amplifiers having a plurality of memory cells connected to each pair of bit lines on the one side, and a pair of bit lines on the other side opposite to the one side; In a dynamic random access memory having an equalization circuit connected between bit lines, a channel of a pair of N-channel transistors constituting the N-type sense amplifier is connected between each of the pair of bit lines on the other side of the serial connection door. Each gate of the pair of N-channel transistors is cross-connected with each pair of bit lines on the one side. Series connected in common of said pair of yen channel transistor is a dynamic sense amplifier enhyeong of random access memory, it characterized in that there is connected to the activating transistor for activating the sense amplifier enhyeong 제1항에 있어서, 상기 배리어 트랜지스터는 낮은 전원전압을 제어전압으로 사용함을 특징으로 하는 엔형센스앰프.The n-type sense amplifier of claim 1, wherein the barrier transistor uses a low power supply voltage as a control voltage. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038071A 1994-12-28 1994-12-28 Sense amp circuit KR0143028B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940038071A KR0143028B1 (en) 1994-12-28 1994-12-28 Sense amp circuit
TW084111313A TW278241B (en) 1994-12-28 1995-10-26 Sense amplifying circuit
JP7315391A JPH08235863A (en) 1994-12-28 1995-12-04 Sense amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038071A KR0143028B1 (en) 1994-12-28 1994-12-28 Sense amp circuit

Publications (2)

Publication Number Publication Date
KR960025758A true KR960025758A (en) 1996-07-20
KR0143028B1 KR0143028B1 (en) 1998-08-17

Family

ID=19404400

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038071A KR0143028B1 (en) 1994-12-28 1994-12-28 Sense amp circuit

Country Status (3)

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JP (1) JPH08235863A (en)
KR (1) KR0143028B1 (en)
TW (1) TW278241B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100248868B1 (en) * 1996-12-14 2000-03-15 윤종용 Flash non-volatile semiconductor memory device and its operating mode controlling method
JP5248019B2 (en) 2007-01-09 2013-07-31 エルピーダメモリ株式会社 Semiconductor memory device and sense amplifier circuit thereof

Also Published As

Publication number Publication date
TW278241B (en) 1996-06-11
KR0143028B1 (en) 1998-08-17
JPH08235863A (en) 1996-09-13

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