KR960019610A - Spacer insulating layer formation method - Google Patents

Spacer insulating layer formation method Download PDF

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Publication number
KR960019610A
KR960019610A KR1019940030959A KR19940030959A KR960019610A KR 960019610 A KR960019610 A KR 960019610A KR 1019940030959 A KR1019940030959 A KR 1019940030959A KR 19940030959 A KR19940030959 A KR 19940030959A KR 960019610 A KR960019610 A KR 960019610A
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KR
South Korea
Prior art keywords
insulating layer
spacer
forming
spacer insulating
ion implantation
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Application number
KR1019940030959A
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Korean (ko)
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KR0167603B1 (en
Inventor
유상호
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940030959A priority Critical patent/KR0167603B1/en
Publication of KR960019610A publication Critical patent/KR960019610A/en
Application granted granted Critical
Publication of KR0167603B1 publication Critical patent/KR0167603B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 스페이서 절연층 형성방법에 관한 것으로, 스페이서 절연층에 의해 야기되는 모서리 부분에서의 응력을 이완시킴과 동시에 소스/드레인 이온주입시 형성되는 비정질층 형상을 반달형으로 하여 에피택셜 성장된 실리콘층 형성시 결합을 제거하는 스페이서 절연층 형성방법에 관한 것이다.The present invention relates to a method for forming a spacer insulating layer, wherein the silicon layer epitaxially grown by relaxing the stress in the corner portion caused by the spacer insulating layer and at the same time forming the amorphous layer formed during the source / drain ion implantation into a half moon shape. The present invention relates to a method for forming a spacer insulating layer for removing a bond during formation.

Description

스페이서 절연층 형성방법Spacer insulating layer formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 일실시예에 따른 스페이서 절연층 형성 공정 단면도.Figure 2 is a cross-sectional view of the spacer insulating layer forming process according to an embodiment of the present invention.

Claims (4)

반도체 소자 제조공정 중 특정 패턴의 측벽에 형성되는 스페이서 절연층 형성방법에 있어서, 상기 스페이서 절연층을 완만한 곡선의 S자 형으로 형성하는 것을 특징으로 하는 스페이서 절연층 형성방법.A method of forming a spacer insulating layer formed on sidewalls of a specific pattern during a semiconductor device manufacturing process, wherein the spacer insulating layer is formed in an S-shape with a gentle curve. 제1항에 있어서, 상기 스페이서 절연층은 불순물 도핑 농도에 따른 식각선택비 차이에 따라 형성되는 것을 특징으로 하는 스페이서 절연층 형성방법.The method of claim 1, wherein the spacer insulation layer is formed according to an etching selectivity difference according to an impurity doping concentration. 제2항에 있어서, 상기 스페이서 절연층은 스페이서 절연층이 형성될 특정 패턴 상부에 절연층을 형성하는 단계; 상기 특정 패턴 부위를 제외한 절연층에 불순물을 선택적으로 이온주입하는 단계; 상기 절연층을 블랭킷 식각하여 스페이서를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 스페이서 절연층 형성방법.The method of claim 2, wherein the spacer insulation layer comprises: forming an insulation layer on a specific pattern on which the spacer insulation layer is to be formed; Selectively ion implanting impurities into the insulating layer except for the specific pattern portion; Forming a spacer by blanket etching the insulating layer. 제3항에 있어서, 상기 절연층에 불순물을 선택적으로 이온주입하는 단계는 사영비정이 절연층 전체 두께의 1/3이 되도록 이온주입 하는 단계; 사영비정이 절연층 전체 두께의 1/2이 되도록 이온주입 하는 단계를 포함하여 이루어지는 것을 특징으로 하는 스페이서 절연층 형성방법.The method of claim 3, wherein the ion implantation of the impurity selectively into the insulating layer comprises ion implantation such that the projection ratio is 1/3 of the total thickness of the insulating layer; A method of forming a spacer insulating layer, comprising the step of ion implantation such that the projection projection is 1/2 of the total thickness of the insulating layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940030959A 1994-11-23 1994-11-23 Method for fabricating mosfet KR0167603B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940030959A KR0167603B1 (en) 1994-11-23 1994-11-23 Method for fabricating mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940030959A KR0167603B1 (en) 1994-11-23 1994-11-23 Method for fabricating mosfet

Publications (2)

Publication Number Publication Date
KR960019610A true KR960019610A (en) 1996-06-17
KR0167603B1 KR0167603B1 (en) 1999-02-01

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Application Number Title Priority Date Filing Date
KR1019940030959A KR0167603B1 (en) 1994-11-23 1994-11-23 Method for fabricating mosfet

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100712486B1 (en) * 2000-09-09 2007-04-30 삼성전자주식회사 Control method of etching selectivity using ion implantation

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KR0167603B1 (en) 1999-02-01

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