KR960019592A - How to Reduce Impurity Concentrations on Wafers - Google Patents

How to Reduce Impurity Concentrations on Wafers Download PDF

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Publication number
KR960019592A
KR960019592A KR1019940031600A KR19940031600A KR960019592A KR 960019592 A KR960019592 A KR 960019592A KR 1019940031600 A KR1019940031600 A KR 1019940031600A KR 19940031600 A KR19940031600 A KR 19940031600A KR 960019592 A KR960019592 A KR 960019592A
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KR
South Korea
Prior art keywords
wafer
atmosphere
predetermined time
effect
heat
Prior art date
Application number
KR1019940031600A
Other languages
Korean (ko)
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KR100312971B1 (en
Inventor
엄금용
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940031600A priority Critical patent/KR100312971B1/en
Publication of KR960019592A publication Critical patent/KR960019592A/en
Application granted granted Critical
Publication of KR100312971B1 publication Critical patent/KR100312971B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Abstract

본 발명은 수소(H2) 분위기에서 소정 시간동안 웨이퍼를 열처리하는 제1단계; 및 산소(O2) 분위기에서 소정 시간동안 열처리하는 제2단계를 포함하는 것을 특징으로 하며, 첫째, 자연산화막의 제거효과가 있고, 둘째, 웨이퍼의 표면 및 표면 근처에 잔재하는 불순물, 특히 산소의 외부 확산효과, 세째, 웨이퍼 표면에 잔존하는 금속성불순물에 대한 개더링효과, 네째, 웨이퍼 벌크내의 분순물을 외부 확산시켜 이후 열공정을 거치면서 외부 확산되어 BMD(Bulk Micro Defect)의 원인이 되는 불순물을 제거하는 효과 등이 있는 웨이퍼에서의 불순물 농도 감소 방법에 관한 것이다.The present invention comprises a first step of heat-treating the wafer for a predetermined time in a hydrogen (H 2 ) atmosphere; And a second step of heat-treating for a predetermined time in an oxygen (O 2 ) atmosphere. First, there is a removal effect of the natural oxide film. External diffusion effect, third, gathering effect on metallic impurities remaining on the wafer surface, and fourth, external impurities are diffused in the wafer bulk and then diffused outside during thermal process to remove impurities that cause BMD (Bulk Micro Defect). The present invention relates to a method for reducing impurity concentration in a wafer having a removing effect.

Description

웨이퍼에서의 불순물 농도 감소 방법How to Reduce Impurity Concentrations on Wafers

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

Claims (5)

수소(H2) 분위기에서 소정 시간동안 웨이퍼를 열처리하는 제1단계; 및 산소(O2) 분위기에서 소정 시간동안 열처리하는 제2단계를 포함하는 것을 특징으로 하는 웨이퍼에서의 불순물 농도 감소 방법.A first step of heat-treating the wafer in a hydrogen (H 2 ) atmosphere for a predetermined time; And a second step of heat-treating for a predetermined time in an oxygen (O 2 ) atmosphere. 제1항에 있어서, 상기 제1단계는, 적어도 1000℃의 수소(H2) 분위기에서 소정 시간동안 열처리하는 것을 특징으로 하는 웨이퍼에서의 불순물 농도 감소 방법.The method of claim 1, wherein the first step is heat treatment for a predetermined time in a hydrogen (H 2 ) atmosphere of at least 1000 ℃. 제2항에 있어서, 상기 열처리는 30 내지 60분 동안 실시하는 것을 특징으로 하는 웨이퍼에서의 불순물 농도 감소 방법.The method of claim 2, wherein the heat treatment is performed for 30 to 60 minutes. 제1항에 있어서, 상기 제2단계는, 적어도 900 내지 950℃, 산소(O2) 분위기에서 소정 시간동안 열처리하는 것을 특징으로 하는 웨이퍼에서의 불순물 농도 감소 방법.The method of claim 1, wherein the second step is a heat treatment for at least 900 to 950 ° C. for a predetermined time in an oxygen (O 2 ) atmosphere. 제4항에 있어서, 상기 열처리는 0.5 내지 1.5시간 동안 실시하는 것을 특징으로 하는 웨이퍼에서의 불순물 농도 감소 방법.The method of claim 4, wherein the heat treatment is performed for 0.5 to 1.5 hours. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940031600A 1994-11-28 1994-11-28 Method for reducing oxygen impurity density inside silicon wafer KR100312971B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940031600A KR100312971B1 (en) 1994-11-28 1994-11-28 Method for reducing oxygen impurity density inside silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940031600A KR100312971B1 (en) 1994-11-28 1994-11-28 Method for reducing oxygen impurity density inside silicon wafer

Publications (2)

Publication Number Publication Date
KR960019592A true KR960019592A (en) 1996-06-17
KR100312971B1 KR100312971B1 (en) 2002-04-06

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KR1019940031600A KR100312971B1 (en) 1994-11-28 1994-11-28 Method for reducing oxygen impurity density inside silicon wafer

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100323061B1 (en) * 1999-08-24 2002-02-07 이 창 세 Method of grown-in defects reduction on the surface and near surface of silicon wafer
KR100532939B1 (en) * 1999-09-29 2005-12-02 매그나칩 반도체 유한회사 Method for forming substrate of semiconductor device
KR100780843B1 (en) * 2006-08-28 2007-11-30 주식회사 실트론 High quality substrate by high temperature process for device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0828353B2 (en) * 1988-12-28 1996-03-21 東芝セラミックス株式会社 Silicon wafer with protective coating for storage and method of forming protective coating for storage of silicon wafer
JP2801704B2 (en) * 1989-12-11 1998-09-21 株式会社東芝 Semiconductor substrate manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100323061B1 (en) * 1999-08-24 2002-02-07 이 창 세 Method of grown-in defects reduction on the surface and near surface of silicon wafer
KR100532939B1 (en) * 1999-09-29 2005-12-02 매그나칩 반도체 유한회사 Method for forming substrate of semiconductor device
KR100780843B1 (en) * 2006-08-28 2007-11-30 주식회사 실트론 High quality substrate by high temperature process for device and manufacturing method thereof

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Publication number Publication date
KR100312971B1 (en) 2002-04-06

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