KR960016379B1 - Wide band width, high separation, low insertion loss scatter type switch circuit - Google Patents

Abstract

the first FET(T1) connected to the input terminal; the first coil(L1) connected to the first FET; the second coil(L2) connected to the first coil; the second FET(T2) connected between the connection of L1 and L2 and the ground; the third coil(L3) connected to the second coil; the third FET(T3) connected between the connection of L2 and L3 and the ground; the forth coil(L4) connected to the third coil; the forth FET(T4) connected between the connection of L3 and L4 and the ground; and the fifth FET(T5) connected between L4 and the ground.

Description

Broadband high isolation and low insertion loss distributed switch circuit

1 is a block diagram of a prior art.

2 is a circuit diagram according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

L1 to L4: Coil T1 to T5: MESFET

The present invention relates to a distributed switch circuit having broadband high isolation and low insertion loss characteristics used in a broadband transmission / reception module.

1 is a view of the prior art, Figure 1 (a) is a single FET switch circuit of the series connection, Figure 1 (b) is a schematic diagram of a single FET switch circuit of the parallel connection, T in the drawing is a MESFET. Indicates. The operation states of the single FET switch circuit of the series connection shown in (a) of FIG. 1 and the single FET switch circuit of the parallel connection shown in (b) of FIG. 1 are clearly compared and explained. same.

TABLE 1

In the case of the conventional paralleled or series-connected single FET switch circuit having the above operating characteristics, the operating frequency band is limited and the maximum input / output isolation characteristic is about -18dB. As such, the increased insertion loss of the shunt array FET switching circuit as the frequency increases and the isolation isolation in the series-connected FET switch are the cache between the drain sources that occur when the FET is biased (│VG│> │Vpinchoff│). This is due to signal leakage through the tance component (hereinafter referred to as Cds).

Accordingly, an object of the present invention is to provide a vastly high isolation and low insertion loss distributed switch circuit, which is designed to solve the problems of the prior art and is configured to have excellent isolation characteristics and minimize insertion loss.

In order to achieve the above object, the present invention provides a switching circuit for a wideband transceiver module, comprising: a first FET connected to an input terminal, a first coil connected to the first FET, a second coil connected to the first coil, and the first coil; A second FET connected between the connection points of the first and second coils and the dish, a third coil connected to the second coil, a third FET connected between the connection points of the second and third coils and a ground, and the third coil. And a fourth coil connected to each other, a fourth FET connected between the connection points of the third and fourth coils and a ground, and a fifth FET (T5) connected between the fourth coil and the output terminal to operate in an artificial transmission line structure. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic diagram of a preferred embodiment according to the present invention, in which T1 to T5 represent switching means composed of MESFETs, and L1 to L4 represent coils, respectively.

In general, when the current blocking degree between the drain and the source of the MESFET used as the switch is increased, the isolation between the drain source is increased. At this time, the resistance Rds between the drain sources usually has a resistance value of about 2 KΩ, but as the frequency increases, the resistance of the capacitor Cds between the drain sources decreases gradually, and the total resistance of the sum of the resistances of Rds and Cds decreases. As such, if the overall resistance between the drain sources is reduced, the isolation between the drain sources may not be performed properly, and the isolation characteristics will be degraded.

Therefore, in order to reduce the overall resistance reduction between drain sources due to Cds at high frequencies, the effect of Cds must be eliminated at the operating frequency. For this purpose, connecting the inductance L between the drain and the source can resonate the Cds at the operating frequency.

However, if the inductance value is fixed, the resonance band cannot be satisfied by the change of frequency, so this method has a limited resonance band.

Therefore, in one embodiment according to the present invention, the circuits are configured by periodically arranging the MESFETs T1 to T5 and the coils L1 to L4, which are switching means, to have an artificial transmission line structure as shown in FIG. Is absorbed by the artificial transmission line structure.

That is, the present invention includes a first MESFET T1 connected to an input terminal, a first coil L1 connected to the first MESFET T1, a second coil L2 connected to the first coil L1, and the first coil. The second MESFET T2 connected between the connection points of the first and second coils L1 and L2 and the ground, the third coil L3 connected to the second coil L2, and the second and third coils L2. And a third MESFET T3 connected between the connection point of L3 and the ground, the fourth coil L4 connected to the third coil L3, and the connection point and ground of the third and fourth coils L3 and L4. And a fourth MESFET T4 connected therebetween, and a fifth MESFET T5 connected between the fourth coil L4 and an output terminal.

The present invention configured as described above specifically has the following design and operating conditions.

Here, RON is an internal resistance when the MESFETs (T1 to T5) are turned on, rg is an internal resistance of the gate, and Cg is a capacitor of the gate. In addition, it is preferable that the inductance values of L1 and L4 are the same, the inductance values of L2 and L3 are the same, and the inductance values of L1 and L4 are set to be twice the inductance values of L2 and L3.

The ON switching state between input and output is VG1 = 0V, | VG2 |> | Vpinchoff |, and the OFF switching state between input and output is | VG2 |> | Vpinchoff |, and VG2 = 0V.

The present invention configured according to the above design conditions and operating conditions, the low frequency isolation reduced by the periodically connected coils (L1 to L4) to be improved by two MESFETs (T1 and T5) connected in series with the input terminal and the output terminal. Three MESFETs (T2 through T4), shunted, improve high frequency isolation. In addition, the present invention operates as a bidirectional switch, and because of the artificial transmission line structure, impedance matching can be minimized over a wide band, thereby minimizing signal reflection.

That is, as can be seen in Figure 2, the vastly high isolation and low insertion loss distributed switch circuit according to the preferred embodiment of the present invention is not an actual transmission line, but an actual transmission line structure in which high frequency signals are desired to pass using L and C. The artificial transmission line structure is approximated by Z0 and Z0 is the characteristic impedance of the artificial transmission line. At this time, since the characteristic impedance Z0 of the artificial transmission line is not a function of frequency, it is possible to match with an external circuit over a wide bandwidth. Therefore, signal reflection is minimized.

Experimental results to examine the effect of the present invention, when using a MESFET having a gate length of 0.5㎛, the gate width of 1mm was confirmed to have excellent isolation characteristics of less than -70dB over about 2 ~ 20GHz.

Therefore, the present invention configured and operated as described above has the effect of having high isolation and low insertion loss over a wide bandwidth.

Claims (4)

A switching circuit used for a wideband transceiver module; A first FET T1 connected to the input terminal; A first coil L1 connected to the first FET T1; A second coil L2 connected to the first coil L1; A second FET (T2) connected between a connection point of the first and second coils (L1, L2) and ground; A third coil L3 connected to the second coil L2; A third FET (T3) connected between the connection point of the second and third coils (L2, L3) and ground; A fourth coil L4 connected to the third coil L3; A fourth FET T4 connected between the connection points of the third and fourth coils L3 and L4 and ground; And a fifth FET (T5) connected between the fourth coil (L4) and an output terminal to operate in an artificial transmission line structure. 2. The high isolation and low insertion loss distributed switch circuit according to claim 1, wherein the second coil (L2) and the third coil (L3) have the same size. 3. The high isolation and low insertion loss distributed switch circuit according to claim 2, wherein the first coil (L1) and the fourth coil (L4) have the same size. 4. The high isolation and low insertion loss distributed switch according to claim 3, wherein the first and fourth coils L1 and L4 are twice as large as the second and third coils L2 and L3. Circuit.