KR960016272B1 - Double making processor - Google Patents

Abstract

The apparatus comprises an error sensing/processing apparatus on an operation part and the same on a stand-by part. The apparatus on the operation part comprises: a data and address-buffering means(21) transmitting data and address to the operation part; a buffer control means(22) which outputs a buffer control signal to the buffering means(21) and outputs a control signal to the stand-by part; an address latch means(26) which latches the next address after receiving a transmission-verifying signal, and maintaining the present address if receiving an error signal; a mode control means(24) controlling the doubling operation type; a main processor-inspecting means(25) inspecting a main processor; an error-sensing and processing means(27) outputting an error signal and an error interrupt signal; and a data transmission-verifying means(23) which outputs a transmission-verifying signal if receiving a write completion signal, and outputs an error signal otherwise.

Description

Error Detection / Processing Device of Redundant Processor and Its Method

1 is a connection structure diagram of an error sensing / processing device of a redundant processor according to the present invention.

2 is a block diagram of an error detection / processing device of a redundant processor according to the present invention.

3 is an error detection / processing flow chart in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

1,1 ': Main processor board 2,2': I / O board

3,3 ': Error detection / processing device of redundant processor

21: data and address buffer unit 22: buffer control unit

23: data transmission check unit 24: mode control unit

25: main processor monitoring unit 26: address latch unit

27: error detection and processing unit

The present invention detects and handles an error that occurs when an operating main processor accesses a standby memory when an operating main processor abnormally operates among functions of a redundant processor operating in an electronic / exchange type. An error detection / processing device and a method thereof are provided.

Conventionally, in the case of an error of a board having a central processing unit (CPU), there is a difficulty in detecting and processing the same.

The present invention has been made to solve the above problems of the prior art, the expansion of the system bus and the main processor so that the operating main processor can access the operation / standby memory at the same time, respectively, in the processor of the electronic switching system operating in redundancy An object of the present invention is to provide an error detecting / processing device and a method for monitoring the normal operation of the system.

An apparatus of the present invention for achieving the above object is, in the error detection / processing apparatus of the redundant processor having the same structure of the operating error detection / processing device and the standby error detection / processing device, the operation error detection / processing The apparatus comprises: data and address buffering means for receiving data and addresses via a system bus and transmitting data and addresses to the standby error detection / processing apparatus in accordance with a buffer control signal; Buffer control means for outputting a buffer control signal to said data and address buffering means by a control signal of a system bus and for outputting a control signal to said standby error detection / processing device; Address latch means for latching a next address upon receiving a data transfer confirmation signal after receiving an address through a system bus and maintaining the address until a normal completion point when writing a standby memory, and holding a current address upon receiving an error signal; Mode control means for controlling the duplex operation mode to an operation / standby state; Main processor monitoring means for monitoring the main processor; When receiving a standby error signal, an error signal is output to the address latch means, an error interrupt signal is output to the main processor, and the mode control means receives an output signal of the presence or absence of a redundancy mode change and monitors whether there is an error on mode change. If an error occurrence is detected, an error interrupt signal is output to the main processor and the standby error detection / processing device, and the output of the main processor monitoring means is received and the normal operation of the main processor is monitored to detect an error occurrence. Error detection and processing means for outputting an error interrupt signal to said standby side error detection / processing device and a main processor so that duplication switching is performed; And a data transfer confirmation means for outputting a data transfer confirmation signal to the address latch means when receiving a write completion signal from the standby error detection / processing device, and outputting an error signal to the error detection and processing means if there is no write completion signal. The standby error detection / processing device has the same structure as the operation side error detection / processing device but operates in reverse.

In addition, the method of the present invention, in the error detection / processing method applied to the error detection / processing apparatus of the redundant processor, when the power is turned on (Booter ROM) embedded in the main processor board on both sides A first step of determining a redundancy state by performing communication between the two main processor boards in a redundancy program of a viewr ROM after a program is executed to perform initialization; When the operation / standby state is determined in the first step, after both the operating system and the user application program are loaded and initialized through each of the input / output boards, the operation side executes the program, and the standby side performs a dummy loop to perform the standby operation. Performing a loop); When the main processor of the operating side detects a write error during the simultaneous operation / standby data in memory and the standby write error is detected by the processing unit, it reads the address latched by the address latch unit and uses the standby write function in the redundant mode once again. If the data is written normally and the data is written normally, the program is executed normally.In case of a data write error, the duplex mode is changed to single mode, and the operating side continues to execute the program, and the standby side executes the viewer program after the operator's action. A third step of operating as a standby in a duplication mode; And when an operation other than the standby write error is detected by the error detection and processing unit during the operation / standby simultaneous write of data to the memory, the operation main processor sends a transfer signal to the standby side, and the standby side receives the transfer signal. CPU) In case of error, it executes the program by changing the mode from standby to operation, and in case of malfunction of other board, it executes the program by receiving the counter of the program currently running on the board of the main processor of the operating side and the data necessary for program execution. It includes a fourth step.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a connection structure diagram of an error sensing / processing device of a redundant processor according to the present invention, in which 1, 1 'is a main processor board, 2.2' is an input / output (I / O) board, and 3, 3 'is a redundant processor. Each error detection / processing device is shown.

Each board on the operating and standby sides has the same internal structure, and each board is matched to the system bus to communicate with the main processor board.

The operating system bus and the standby system bus are separated from each other by the error detection / processing device of the redundant processor, and the error detection / processing device of the redundant processor is designed to have an extension function of the system bus.

In general operation, when the user turns on the power, the main processor board's booter first initializes the CPU and peripherals, and then communicates with the other main processor board to get the operation / standby state. The operation and standby main processor (1,1 ') is operated by loading the operating system and the application program of the user through the input / output (I / O) board (2,2') After initializing the peripheral devices necessary for the operation of the system with the defined data, the operating main processor (1) operates the redundancy processing routine program of the operating system to check the redundancy mode status of the error detection / processing device (3) of the redundant processor. Writing to the mode register of the mode control unit activates / standby.

At this time, the duplex operation mode has four types.

The first is the reading of the operating memory and most of the normal program execution. The second is the reading of the standby memory. In this case, the data of the operating memory and the data of the standby memory are compared to determine whether the data match. The third mode is used to write the standby data. When the operation / standby data inconsistency occurs, it is used to check the mismatched standby address and read the operation data to write the data to the standby. Simultaneous write / waiting. This is a duplication mode in which the operating system writes data to the operating memory and writes to the standby memory at the same time.

2 is a block diagram of an error detection / processing device of a redundant processor according to the present invention, in which 21 is a data and address buffer unit, 22 is a buffer control unit, 23 is a data transmission confirmation unit, 24 is a mode control unit, and 25 is a main unit. The processor monitoring unit, 26 denotes an address latch unit, and 27 denotes an error detecting and processing unit, respectively. Since the two redundant processor error detecting / processing units have the same structure, only the error detecting / processing unit of the operation side redundant processor will be described.

As shown in the figure, the error / sensing processing apparatus 3 of the redundant processor receives data and an address through a system bus, and transmits data and addresses to the other redundant processor error sensing / processing apparatus according to the buffer control signal. And an address buffer unit 21, a buffer control unit 22 for outputting a buffer control signal to the data and address buffer unit 21 according to a control signal of a system bus, and outputting a control signal to a counterpart redundant processor error detection / processing device. When the address is input through the system bus, the corresponding address is maintained until the normal completion point when writing to the standby memory, and when the data transmission confirmation signal is received, the next address is latched, and when the error signal is received from the error detection and processing unit 27, the current address is received. Address latch section 26 for holding the Outputs an error signal to the address latch unit 26 when an error signal is received from the mode control unit 24 for controlling the standby / standby state, the main processor monitoring unit 25 for monitoring the main processor, and the data transmission confirmation unit 23. And outputs an error interrupt signal to the main processor, receives an output signal of the presence or absence of a redundancy mode change from the mode control unit 24, monitors the presence or absence of an error on mode change, and detects an error occurrence. Outputs the signal, and receives the output of the main processor monitoring unit 24 and monitors the normal operation of the main processor to detect an error occurrence. The error interrupt signal is transmitted to the counterpart redundant processor error detection / processing device 3 'and the main processor. When the error detection and processing unit 23 to output a signal to quickly perform a redundancy transfer, and receives a write completion signal from the standby device And a data transfer confirmation unit 23 for outputting a data transfer confirmation signal to the address latch unit 26 and outputting an error signal to the error detection and processing unit 27 when there is no write completion signal.

When the main processor writes data and address and control signals to the system bus used for communication between the main processor board (1) and other boards, the error detection / processing unit (3) of the redundant processor on the operating side receives the control signals of the system bus. Data and address to the data and address buffer unit 21 '(not shown) of the error detection / processing device of the standby redundant processor under the data and address buffer unit 21 under the control of the buffer controller 22 receiving the input. Send it. Thereafter, when the standby side redundant processor error detection / processing device 3 'writes data to the memory according to the operation side control signal, the data write completion signal of the standby side memory is transmitted to the operation side data transfer confirming unit 23 to perform operation / The write of the wait is completed.

At this time, the operating main processor board 1 ends the execution cycle when the data of the operating memory is correctly written, and the next cycle is performed. After the address latch unit 26 latches an address in the error detection / processing apparatus 3 of the operation side redundant processor for accurate writing of the standby data, the write completion signal of the standby memory is transmitted to the data transfer confirmation unit 23. Is detected, the data transfer confirmation unit 23 outputs a data transfer confirmation signal to the address latch unit 26, and the address latch unit 26 latches the next write address.

However, if the data write completion signal of the standby memory is not detected by the data transfer confirmation unit 23, the error signal is transmitted to the error detection processing unit 27, and the error detection and processing unit 27 uses the defined interrupt signal as the main processor. Informs the board 1 of an error in the standby processor and outputs an error signal to the address latch unit 26. The main processor board 1 is an address latch unit 26 of the redundant processor error detection / processing apparatus 3. Reads the address latched in the) and rewrites the data. If the correct data is not written even during rewriting, the state of the duplication mode is shifted to the state of the redundancy and the system operator is informed of the current processor state so that the operator can take action. At this time, the operation side continues to operate normally, but the standby side is turned down by using the system reset signal.

The main processor supervisor 25 is a means for monitoring the normal operation of the main processor board 1 on the operating side, and the operating main processor board continues in an infinite loop due to an error of an operating system and a user application. If it detects the operation and notifies the error detecting and processing unit 27, the error detecting and processing unit 27 notifies the standby main processor of the inoperable state of the operating main processor regardless of the main processor so that the standby side operates. At the same time, the operating side sends a reset signal to the main processor board to be down. The main processor monitoring unit 25 is configured using a register and an adjustable timer, and an error signal is generated if the operating main processor board 1 does not access the register within a set time, and the error detection and processing unit 27 The program consists of array logic (PAL).

3 is an error detection / processing flow chart according to the present invention.

First, when the user turns the power ON, the program is executed by the viewr ROM embedded in the main processor boards 1 and 1 'on both sides (31), so that the CPU and the peripheral device When initialized, the redundancy program of the viewer ROM communicates between the two main processor boards, and when the redundancy state is determined (32), the operating system and the user application are loaded through the input / output boards (2, 2 ') on both sides of the operation / standby (33). 42) After performing device initialization (34, 43) with the operation data of the device defined in the operating system, the operating program is executed (35), and the standby program is the main processor for performing the standby operation after the device initialization (43). The board performs only a dummy loop (44).

At this time, if an error other than the write error is detected by the error detection and processing unit 27 during the operation / standby simultaneous write of data to the memory for the execution of the program, if the main processor sends a switching signal to the standby, the standby write error Is detected (36), the main processor board reads the address latched by the address latch unit 26, and writes data once again using the standby write function during the redundancy mode (38). If the program continues to run after the program is terminated (40), and in the case of a data write error, the duplex mode is changed to a single mode (39), and the operating side continues to execute the program and informs the operator of the system status. The viewer program is executed again from the beginning to operate in the standby of the duplication mode (41).

If there is no access of the operating main processor board 1 for a time defined by the corresponding register defined in the main processor monitoring unit 25, the main processor error is determined and the error detection and processing unit 27 is notified. In this case, the standby main processor sends an operation signal to the standby main processor, and the standby main processor changes its operation according to the error of the operating central processing unit (CPU), the operating power supply and the board malfunction (45). In case of an error, the program immediately proceeds to operation and terminates (46).

At this time, the previous operating side may transmit the main processor board system reset signal by the error / detection processing unit (3, 3 ') of the redundant processor. Inform the processor status so that the operator takes action and restarts from the beginning to operate in normal standby.

In case of a functional disorder of another board, the receiver prepares to receive the counter of the program currently running on the main processor board of the operating board and the data necessary for the program execution (47). ).

Accordingly, the present invention constructed and operated as described above continuously generates the pre-data write end signal on the operation side regardless of the standby data write during operation / standby simultaneous write in the processor device operating / standby to continue the next cycle. This not only improves performance and detects write-side errors, but also detects whether the main processor board is operating normally.

Claims (2)

In an error detection / processing device of a redundant processor in which an operation side error detection / processing device and a standby side error detection / processing device have the same structure, the operation side error detection / processing device inputs data and an address via a system bus. Data and address buffering means for receiving and transmitting data and an address to the standby error detection / processing device according to a buffer control signal; Buffer control means for outputting a buffer control signal to said data and address buffering means by a control signal of a system bus and for outputting a control signal to said standby error detection / processing device; Address latch means for latching a next address upon receiving a data transfer confirmation signal after receiving an address through a system bus and maintaining the address until a normal completion point when writing a standby memory, and holding a current address upon receiving an error signal; Mode control means for controlling the duplex operation mode to an operation / standby state; Main processor monitoring means for monitoring the main processor; When receiving a standby error signal, an error signal is output to the address latch means, an error interrupt signal is output to the main processor, and the mode control means receives an output signal of the presence or absence of a redundancy mode change and monitors whether there is an error on mode change. If an error occurrence is detected, an error interrupt signal is output to the main processor and the standby error detection / processing device, and the output of the main processor monitoring means is received and the normal operation of the main processor is monitored to detect an error occurrence. Error detection and processing means for outputting an error interrupt signal to said standby side error detection / processing device and a main processor so that duplication switching is performed; And a data transfer confirmation means for outputting a data transfer confirmation signal to the address latch means when receiving a write completion signal from the standby error detection / processing device, and outputting an error signal to the error detection and processing means if there is no write completion signal. And the standby error detecting / processing device has the same structure as the operating side error detecting / processing device but operates in reverse. In the error detection / processing method applied to the error detection / processing device of the redundant processor, when the power is turned on, the program is executed by the booter ROM embedded in both main processor boards to perform initialization. A first step of determining a redundancy state by performing communication between the two main processor boards in a redundancy program of the viewr ROM; When the operation / standby state is determined in the first step, after both the operating system and the user application program are loaded and initialized through each of the input / output boards, the operation side executes the program, and the standby side performs a dummy loop to perform the standby operation. Performing a loop); When the main processor of the operating side detects a write error during the simultaneous operation / standby data in memory and the standby write error is detected by the processing unit, it reads the address latched by the address latch unit and uses the standby write function in the redundant mode once again. If the data is written normally and the data is written normally, the program is executed normally.In case of a data write error, the duplex mode is changed to single mode, and the operating side continues to execute the program, and the standby side executes the viewer program after the operator's action. A third step of operating as a standby in a duplication mode; And when an operation other than the standby write error is detected by the error detection and processing unit during the operation / standby simultaneous write of data to the memory, the operation main processor sends a transfer signal to the standby side, and the standby side receives the transfer signal. CPU) In case of error, it executes the program by changing the mode from standby to operation, and in case of malfunction of other board, it executes the program by receiving the counter of the program currently running on the board of the main processor of the operating side and the data necessary for program execution. Error detection / processing method of a redundant processor comprising a fourth step.