KR19990075767A - Fault control method of digital cellular system - Google Patents

Abstract

The present invention is to switch when a failure occurs during the operation of the redundant processor in the control station of the digital cellular system. In the present invention, when the processor fails, the active side copies the current processor state information to the state information storage buffer and completes the transfer preparation. If the flag is turned on to perform error processing, the standby side restores the processor's state information to the data of the active state information storage buffer if the transfer preparation completion flag is turned on, and then restores the independent state information to perform the error processing. This can reduce the coupling that only a specific operating system needs to use, and increase portability and maintenance efficiency to other processors.

Description

Fault control method of digital cellular system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital cellular system, and more particularly, to a method of switching in the event of a failure during operation of a redundant processor in a control station of a digital cellular system.

In general, a mobile communication system is a communication system that targets mobile devices such as people, cars, ships, trains, and airplanes, including mobile phones (mobile phones, vehicle phones), port phones, aircraft phones, and mobile phones (trains, cruise ships). Installed on express buses), radio calling, radiotelephones, satellite mobile communications, and digital cellular systems.

In this case, the digital cellular system adopts a redundancy structure in the main processor for fast recovery in the event of a system failure in order to provide a seamless communication service to mobile subscribers.

1 is a block diagram of a call control block (CCP) in a control station of a general digital cellular system.

As shown in the drawing, an active / standby Active Processor (MPMA) Main Processor & Memory Management Assembly board (MPMA) performing overall processing of a common signal block by a parallel real-time operating system (CROS) ( 11) 21; An active / standby duplication communication control assembly board (DCCA) 12 for controlling communication through a main processor system bus (MPS-bus) according to control of each of the active / standby MPMAs 11 and 21. It consisted of 22.

In the call management block (CCP), which is a common signaling block (CSB), the S-channel is a serial communication channel capable of transmitting / receiving simple redundancy information between the redundant MPMAs 11 and 21. The channel is a message transmission channel managed by the DCCA 12, 22, and can quickly transmit and receive a large amount of duplication information. The D-channel is a high-speed data transmission channel managed by the DCCA 12 and 22 and is for maintaining active and standby memory coincidence (Concurrent Write).

Therefore, CCP, which is a central processor in the control station, is composed of MPMA (11) (21) board and DCCA (12) (22), and the call setting, call release, redundancy method through memory matching function through DCCA (12) (22). Soft hand-off support, hard hand-off support, paging support, selector management, overload control, and more.

In addition, the conventional CCP uses CROS as an operating system, and CROS has a hardware configuration including an MPMA (11) (12) board and a DCCA (12) (22) board employing an MC68030 CPU (Central Processing Unit). It is a developed operating system.

However, such a redundant switching method by CROS is very complicated, the redundant switching is performed by being dependent on a specific CPU, and the operating system must use CROS.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method for controlling a failure of a digital cellular system for switching in case of a failure during operation of a dual processor in a control station of a digital cellular system. To provide.

In order to achieve the above object, the failure control method of the digital cellular system according to the present invention,

An active side failure processing step in which the active side copies the current processor state information to the state information storage buffer and turns on the transfer preparation completion flag to perform failure processing when the processor fails; A standby side failure processing step of checking whether a transfer preparation completion flag is turned on when a failure occurs in the processor and restoring state information of the processor to data of a state information storage buffer of an active side; When the state information of the processor is restored to the data of the active state information storage buffer, the standby side may be configured to perform a fault processing switching step of restoring independent state information to perform fault processing.

1 is a block diagram of a call management block in a typical digital cellular system,

2 is a flowchart illustrating a failure control method of a digital cellular system according to the present invention;

<Explanation of symbols for the main parts of the drawings>

11: active MPMA 12: active DCCA

21: standby MPMA 22: standby DCCA

Hereinafter, an embodiment according to the technical idea of the failure control method of the present invention, the digital cellular system configured as described above is as follows.

2 is a flowchart illustrating a failure control method of a digital cellular system according to the present invention.

As shown in FIG. 2, when the processor fails, the active side copies the current processor state information to the state information storage buffer and turns on the transfer preparation completion flag to perform the failure processing (ST1) (ST4 to ST6). )Wow; A standby side failure processing step (ST2-ST4) of restoring the state information of the processor with the data of the state information storage buffer of the active side by checking whether the transfer preparation completion flag is turned on when the processor fails; When the state information of the processor is restored to the data of the active state information storage buffer, the standby side may include a fault processing switching step (ST7) of restoring independent state information to perform fault processing.

In the standby side error processing step (ST2) (ST3), the transfer matching completion flag setting information by the active side processor is transmitted by the memory matching function to determine whether the manual side change state storage operation of the active side is completed. And restoring the state information of the processor with the manually changed state information data of the active side.

In the failure processing switching step (ST7), the processor state information on the active side is moved to a program position immediately after the copying to the state information storage buffer is performed to restore the independent state information of the standby side processor, and the standby side is activated. It is set to be characterized in that the continuous failure processing operation immediately before the transfer.

Operation of the failure control method of the digital cellular system according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the CCP processor maintains the same memory contents of the active side and the standby side memory during operation through a memory matching function by the DCCA 12 (22). Therefore, when a system failure occurs and redundancy switching is required, the active side stores key state information in memory and the standby side restores state information stored in memory in real time to play an active role. Saving and restoring state information is implemented using the system calls setjmp and longjmp, which are provided by the compiler. Here, setjmp is a system function that copies the current processor state information to a specific region in memory, and longjmp is a system function that restores processor state information to the contents of a specific region in memory.

Therefore, the present invention adopts an asynchronous redundancy scheme in which the standby side processor does not perform a substantial operation but continues operation when the active side processor fails.

Accordingly, when the active side fails during operation and can no longer perform normal operation, the operating system performs a redundancy switchover. At this time, the active side should quickly pass its status information to the standby side to perform the execution without interruption. The active side stores its state information and informs the standby side by a predetermined method. When the standby operation is completed, the standby side restores the stored state information and performs an active operation.

Since the memory change function of the active side is immediately reflected on the standby side by the memory matching function of the DCCA (12) 22, the CCP stores the state information necessary for the redundancy transfer in the memory, and the standby side restores it when the failure occurs. You can make yourself active. However, recovery should be done very quickly in case of failure, so the status information to be saved and restored during transfer should be minimal.

Here, the status information (Context) may be classified as manual change status information, automatic change status information, and independent status information. The manual change status information is not known unless the information is transferred from the active side. The auto change status information is status information that is automatically changed by the hardware. The independent status information is self-contained even if information is not transferred from the active side. These are status information that can be recovered.

Therefore, in the case of CCP employing the MC68360 as a CPU, the manual change status information corresponds to the sr, a2-a7 and d2-d7 registers, and the auto change status information corresponds to a memory area capable of memory matching, and the independent status information a0 and a1. The status information of the device that can be driven independently from the registers d0 and d1 is applicable. When a switchover occurs, the standby side only needs to pass the passive change status information of the active side.

The active side should store its status information and notify the standby side. This function can also be processed using the memory matching function. In other words, the active side sets a specific area in the memory and the standby side waits for the area to be set.

Therefore, when a failure that requires switching occurs, interrupts are generated in both MPMAs 11 and 21. If the faulted side is active, the active MPMA 11 stores its status information in the interrupt handler and informs the standby MPMA 11 that the storage is completed through the S-channel. The standby side reads the contents of the active side when the active side completes the saving, restores itself to the active side, and continuously performs the operation immediately before the transfer.

Accordingly, when a failure occurs, an interrupt occurs in the active and standby MPMAs (11) 21, the ActiveFailHandler which is an active failure handler is performed on the active side, and the StandbyFailHandler which is a standby failure handler is performed on the standby side.

Therefore, the active side stores its state information in jbFailSwitch, which is a state information storage buffer through setjmp, informs the standby side, and waits for the effect of the failure without affecting the memory (ST1) (ST4-ST6).

The standby side restores the active processor state through longjmp when the manual change state storage operation of the active side is completed. That is, longjmp (jnFailSwitch, 1) is executed to restore the processor state information to the data of the state information storage buffer and move to the program position immediately after execution of manual change state information storage on the active side (ST2) (ST3). Thus, the independent state information is restored, and the standby side is set to active to perform failure processing (ST7).

Here, setjmp and longjmp are almost identical to setjmp and longjmp provided by the compiler, but since standard setjmp and longjmp save and restore only a part of CPU-dependent state information, appropriate modifications are made to save and restore other dependent state information. Add. In practice, the state information to be saved and restored during a changeover is determined by the compiler, its options, the scope of use inside the processor (eg, whether a memory management device is used), and the conditions at which the actual change occurs.

As described above, the present invention is to perform a redundancy switching method when a failure occurs during operation and redundancy control method by the operating system.

Although preferred embodiments of the present invention have been described above, the present invention may use various changes, modifications, and equivalents. That is, the present invention can be applied not only to digital cellular systems but also to other embedded systems in which a memory matching function by hardware is implemented. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the fault control method of the digital cellular system according to the present invention uses a memory matching function to reduce the coupling that only a specific operating system needs to be used in hardware, and to increase the portability to other processors and the efficiency of maintenance. It will have an effect.

Claims (3)

In the failure control method of the digital cellular system, An active side failure processing step in which the active side copies the current processor state information to the state information storage buffer and turns on the transfer preparation completion flag to perform failure processing when the processor fails; A standby side failure processing step of checking whether a transfer preparation completion flag is turned on when a failure occurs in the processor and restoring state information of the processor to data of a state information storage buffer of an active side; If the state information of the processor is restored to the data of the active state information storage buffer, the standby side comprises a failure processing switching step of performing a failure process by restoring independent state information. The method of claim 1, wherein the standby side fault handling step, The memory matching function receives the transfer preparation completion flag setting information by the active processor, determines whether the manual change status information storage operation of the active party is completed, and restores the status information of the processor using the manually changed status information data of the active party. A failure control method of a digital cellular system, characterized in that for performing. The method of claim 1, wherein the fault processing transfer step, The processor side information on the active side is moved to the program position immediately after the copy to the state information storage buffer is performed to restore the independent state information of the standby side processor, and the standby side is set to active to continuously perform the fault handling operation just before switching. Failure control method of the digital cellular system, characterized in that performed by.