KR960014959A

KR960014959A - Simplified logic tester circuit

Info

Publication number: KR960014959A
Application number: KR1019940028320A
Authority: KR
Inventors: 이규택
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1994-10-31
Filing date: 1994-10-31
Publication date: 1996-05-22

Abstract

본 발명은 간이 로직 테스터 회로에 관한 것으로, 인버터와 세븐 세그먼트를 이용하여 입력핀으로 전원이 공급되면 “1” 문자를 세븐 세그먼트에 디스플레이하고, 입력핀으로 하이레벨 신호가 입력되면 세븐 세그먼트에 “H” 문자를 디스플레이한다. 또한, 입력핀로 로우레벨 신호가 입력되면 세븐 세그먼트에 “L” 문자를 디스플레이하고, 입력핀으로 펄스신호가 입력되면 세븐 세그먼트에 “ㅂ” 문자를 디스플레이하는 제작비용이 저렴하고 간단한 구조로 이루어진 테스터를 제공함으로써, 사용자가 보다 편리하게 조립된 기판의 동작상태를 테스트할 수 있도록 한 것이다.The present invention relates to a simple logic tester circuit, and when a power is supplied to an input pin using an inverter and a seven segment, a "1" character is displayed on the seven segment, and a high level signal is input to the seven segment when the input pin is input. ”Character is displayed. In addition, if the low level signal is input to the input pin, the "L" character is displayed on the seven segments, and if the pulse signal is input to the input pin, the "ㅂ" character is displayed on the seven segments. By providing a user, the user can more conveniently test the operating state of the assembled substrate.

Description

Simplified logic tester circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 바람직한 실시예에 따른 간이 로직 테스터 회로의 개략적인 블럭구성도,1 is a schematic block diagram of a simple logic tester circuit according to a preferred embodiment of the present invention;

제2도는 본 발명에 따른 간이 로직 테스터 회로를 채용한 전체 테스터의 정면도.2 is a front view of the entire tester employing the simplified logic tester circuit according to the present invention.

Claims

In the tester circuit for displaying the contact state of the circuit board to be tested on the basis of the signal input through the input pin attached to the outside through the display means consisting of seven segments, three connected in parallel to the input pin A first circuit means composed of an inverter of which the output of one of the inverters is divided into two; Second circuit means composed of three other inverters each connected in series to the three inverters forming the first circuit means; Third circuit means connected to a resistor having a predetermined value and driving two segments such that said display means displays a test setting state; Output signals of the branched inverters and output signals of three inverters constituting the second circuit means respectively drive the two segments and the remaining segments other than the other segment to display the contact state of the circuit board; And said circuit means comprises one sieve.

※ Note: The disclosure is based on the initial application.