KR960014602B1 - Bit line sense amplifier control circuit of semiconductor device - Google Patents

Abstract

a memory cell array block(11); a bit line sense amplifier array block(12) for sensing and amplifying signal of bit line connected to the memory cell array block(11); a precharge signal generator(15) for comprising a pull-up MOS transistor(MN5) and a pull-down MOS transistor(MN6) and applying a voltage to a pull-up bias line and a pull-down bias line of the bit line sense amplifier array block(12) in advance; and a bit line sense amplifier control circuit(13) for stabilizing the driving current of the bit line sense amplifier array block(12) and connected to the pull-down bias line.

Description

Semiconductor memory device

1 is a block diagram of a conventional semiconductor memory device.

2 is a configuration diagram of a semiconductor memory device of the present invention.

* Explanation of symbols for main parts of the drawings

11: memory cell array block 12: sense amplifier array block

13: bit line sense amplifier control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device which reduces peak current generated during operation of a bit line sense amplifier of a DRAM. In particular, the potential of a power supply voltage line The present invention relates to a semiconductor memory device including a bit line sense amplifier control circuit configured to detect and adjust an operating speed of a sense amplifier.

In general, a process of reading data in a memory device is as follows.

In the memory memory cell array block of the DRAM device, a specific wonder line is selected by an address signal transmitted from the outside of the device, and data is transferred to each bit line BL, / BL from all cells connected to the word line. The data transferred to the bit lines BL and / BL is sensed and amplified by the sense amplifier array block and then output to the outside of the memory device through the data lines DB and / DB and the data output buffer.

In this process, when one word line is enabled, the entire bit line sense amplifier array block operates to sense and amplify the read data. Therefore, the peak current is very large, which causes noise on the power supply line or causes an entire data access time. The problem of longer time occurs.

In order to solve this problem, the present invention initially increases the driving capability of the bit line sense amplifier in order to increase the data sensing speed, and increases the driving current so that the potential of the power voltage line is at an appropriate level. A semiconductor memory device including a bit line sense amplifier control circuit for stabilizing the device by reducing the driving ability of the sense amplifier when lowered below is implemented.

FIG. 1 is a block diagram of a conventional semiconductor memory device, which includes a memory cell array block 11, a bit line sense amplifier array block 12, and a bit line BL, / BL and a bit line sense amplifier driving at a standby time. The precharge signal generator 14 includes a pull-up bias signal and a pull-down bias signal? RTO, /? S at the standby potential VBLp.

Referring to the operation, first, the bit line precharge signal ψBLP in the precharge signal generator 14 is disabled in a logic low state, and when the block select delay signal BSDBSD is enabled to be rosy high, the bitline sense amplifier is activated. The pull-up transistors and the pull-down transistors MP1 and MN1, which are driving transistors, operate to enable the entire bit line sensing amplification array block 12, so that a large amount of current flows instantaneously to generate a high peak current. Noise is caused.

In order to control the peak current, the peak current is controlled by reducing the size of the driving transistor of the bit line sense amplifier or by configuring the pull-down transistor MN1 in multiple stages. However, the method has a problem of limiting the data sensing speed.

Therefore, in the present invention, in order to minimize the data detection speed delay and to adjust the peak current, the potential of the power supply line and the reference potential are detected by comparing the potential of the power supply line with the current flowing as much as possible in the initial stage when the bart sense amplifier operates. It includes a bit line sense amplifier control circuit to improve the detection speed, and to limit the sense amplifier driving current when the potential of the power supply voltage line in the chip is lowered due to the large current consumption to fall below the reference potential affecting the operation of the chip. A bit line sense amplifier control circuit is implemented.

The semiconductor memory device of the present invention for achieving the above object is a bit line detection for sensing and amplifying the signal (BL, / BL) of the bit line connected to the memory cell array block 11 and the memory cell array block 11, respectively An amplifier array block 12, and a pull-up MOS transistor MN5 and a pull-down MOS transistor MN7, which are defined in the pull-up bias signal? RTO and the pull-down bias signal /? S of the bit line sense amplifier array block 12; A precharge signal generator 15 for pre-applying a potential, and a pull-down bias line (/ ψS) of the bit line sense amplifier array block 12 to connect a driving current of the bit line sense amplifier array block 12. And a bit line sense amplifier control circuit 13 for stabilization.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a configuration diagram of a semiconductor memory device of the present invention including the bit line sense amplifier control circuit 13.

The present invention implements a pull-down MOS transistor MN7 in parallel to a pull-down transistor MN6 of a bit line sense amplifier in the same memory cell array block and the related circuit diagram as in FIG. 1, and then operates the pull-down MOS transistor MN7. Is controlled by the output of the bit line sense amplifier control circuit 13 comparing the potential of the reference potential Vref and the power supply voltage line Vcc.

The current limiting circuit 13 for controlling the bit line sense amplifier of the semiconductor memory device is connected between the power supply voltage Vcc and the first node N11, the power supply voltage Vcc and the second node N12, respectively. The first PMOS transistor MP1 and the fourth PMOS transistor MN4 whose gates are commonly controlled by the block select delay signal? BSD, the power supply voltage Vcc, the first node N11, and the power supply voltage Vcc. A second PMOS transistor (MP2) and a third PMOS transistor (MP3) connected between the second node (N12), each gate of which is cross-coupled with the second node (N12), the first node (N11), A first NMOS transistor having a drain connected to a first node N11 and a second node N12, a gate connected to a reference potential Vref and a power supply voltage Vcc, respectively, and having a common source connected thereto. MN1 and the second NMOS transistor MN2 and the first and second NMOS transistors MN1 and MN2 are connected between the common source and the ground voltage. And a third NMOS transistor MN3 whose gate is controlled by the block select delay signal? BSD, the drain of which is connected to the drive signal /? S of the bit line sense amplifier, to the gate of the drive transistor MN7. Apply the output signal.

In addition, the drain of the pull-up MOS transistor MN5 of the precharge signal generator 15 is connected to the power supply voltage Vcc and the source is connected to the pull-up bias signal ψRTO of the sense amplifier array block 12. The source of the pull-down MOS transistor MN6 of the charge signal generator 15 is connected to the ground potential Vss, and the drain thereof is connected to the pull-down bias signal / ψS of the sense amplifier array block 12.

In operation, when the chip is enabled and a specific memory cell array block is selected, the bit line precharge signal ψBLP in the precharge signal generator 15 is disabled and the block of the bit line sense amplifier control circuit 13 is disabled. The selection delay signal? BSD is enabled with logic high to operate the bit line sense amplifier array block 12.

At this time, since the potential of the power supply voltage Vcc is higher than the reference potential Vref at the beginning of the operation of the bit line sense amplifier array block 12, the second node N12 transitions to a logic low, thereby driving transistor. The MN7 operates in conjunction with the transistor MN6 to shift the pull-down bias signal /? S, which is a bit line sense amplifier driving signal, to a logic low state within a short time, thereby increasing the speed of sensing and amplifying data.

The operation of the bit line sense amplifier array block 12 causes the current of the power supply voltage Vcc to fall below the reference potential Vref that will affect the operation of the chip as the current flowing inside the chip flows beyond the design value. Since the two nodes N12 transition to logic high and the pull-down MOS transistor MN7 is turned off, the peak current is limited to a certain value.

Therefore, it becomes possible to operate the bit line sense amplifier array block 12 in a condition close to an optimal state in data sensing.

Although the pull-up MOS transistor and the pull-down MOS transistor described above are used as NMOS transistors, in some cases, PMOS transistors may be used.

As described in FIG. 2, a data sensing operation is realized by implementing a driving transistor connected in parallel to the pull-up driving transistor of the bit line sense amplifier array block 12 and controlling it with the bit line sense amplifier control circuit 13. Peak current and operating speed can be adjusted.

When the bit line sense amplifier control circuit 13 included in the semiconductor memory device of the present invention described above is applied to a DRAM memory device, the size of the driving transistor may be increased in the initial stage of the data sensing operation to increase the sensing operation speed. When the potential of the power supply voltage drops below a certain level, the noise of the power supply line due to the high peak current can be prevented by adjusting the size of the driving transistor with the detected signal, thereby improving reliability of the DRAM memory device. You will get the effect.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (5)

A pull-up bias line and a pull-down of a bit line sense amplifier array block including a memory cell array block, a bit line sensing amplification array block for sensing and amplifying a signal of a bit line connected to the memory cell array block, and a pull-up MOS transistor and a pull-down MOS transistor A precharge signal generator for pre-applying a predetermined potential to a bias line, and a bit line sense amplifier control circuit connected to a pull-down bias line of the bit line sense amplifier array block to stabilize a driving current of the bit line sense amplifier array block. A semiconductor memory device, characterized in that. The first PMOS transistor of claim 1, wherein the bit line sense amplifier control circuit is connected between a power supply voltage and a first node, a power supply voltage and a second node, and each gate is commonly controlled by a block selection delay signal. A 4PMOS transistor, a power supply voltage and a first node, a power supply voltage and a second node connected between the second node and the first node, the second PMOS transistor and the third PMOS transistor and the drain, A first NMOS transistor and a second NMOS transistor, each of which is connected to a first node and a second node, each gate is connected to a reference potential, a power supply voltage, and each source is commonly connected; and the first and second NMOS transistors. A third NMOS transistor connected between a common source of the transistor and the ground voltage and whose gate is controlled by a block select delay signal, and a drain output signal of the second NMOS transistor; A fourth NMOS having a first inverter for receiving a signal; A semiconductor memory device comprising a transistor. The semiconductor memory device of claim 2, wherein the block select delay signal is applied to a pull-up MOS transistor gate of the precharge signal generator through a second inverter. The method of claim 1, wherein the drain of the pull-up MOS transistor of the precharge signal generator is connected to a power supply potential, and the source is connected to a pull-up bias line of the sense amplifier array block, and the source of the pull-down MOS transistor of the precharge signal generator is And a drain connected to a ground potential and a pull-down bias line of the sense amplifier array block. The semiconductor memory device according to any one of claims 1 to 4, wherein the pull-up MOS transistor and the pull-down MOS transistor are NMOS transistors.