KR100278924B1 - Sense Amplifier Driven Bias Potential Precharge Circuit - Google Patents

Abstract

The present invention relates to a sense amplifier driving bias potential precharge circuit which reduces power consumption due to a loss of a threshold voltage when precharging a sense amplifier driving bias potential during a standby operation of a DRAM, and improves precharge operation without increasing the layout. To implement this, a pull-up bias signal line for supplying a power supply potential to a sense amplifier, a pull-down bias signal line for supplying a ground potential to the sense amplifier, and the pull-up when the memory device is in a standby state And a precharge signal line for transmitting a signal for precharging a pull-down bias signal line, and an NMOS transistor for transmitting a precharge potential signal to the pull-up bias signal line by the precharge signal. A precharge signal transfers a precharge potential signal to the pull-down bias signal line And a transfer gate for equalizing the pull-up bias signal line and the pull-down bias signal line by the precharge signal.

Description

Sense Amplifier Driven Bias Potential Precharge Circuit

The present invention relates to a precharge circuit for precharging the sense amplifier driving bias potential of a semiconductor memory device. In particular, the present invention can reduce the power consumption due to a loss of a threshold voltage and can perform a precharge operation quickly without increasing the layout. It relates to an amplifier driving bias potential precharge circuit.

In general, a sense amplifier driving bias potential signal (RTO, / S) for driving a sense amplifier that senses data of a cell in a dynamic random access memory (DRAM) is inverted in standby mode. After precharging to Vdd / 2), the RTO signal rises to the power supply potential Vdd and the / s signal falls to the ground potential Vss. Then, the sense amplifier having a differential amplifier form having a P-channel MOS transistor and an N-channel MOS transistor in a cross-coupled structure is connected to the bit line BL by the driving bias potential signals RTO and / S. A small potential difference of the data contained in / BL) is fed back to spread the potential difference between Vdd and Vss. Then, under the control of the control signal, the RTO / S signal is precharged to Vdd / 2 for the next operation and is in the standby state.

1 illustrates a conventional sense amplifier driving bias potential precharge circuit, in which an NMOS transistor connected between a pull-up bias signal RTO line supplying a power supply potential Vdd to a sense amplifier and a node N1 ( MN2, the NMOS transistor MN1 connected between the node N1 and the bit line precharge potential Vblp line, the bit line precharge potential Vblp line, and the sense amplifier to a ground potential Vss. It consists of an NMOS transistor MN3 connected between the pull-down bias signal (/ S) lines supplying. The NMOS transistors MN1 to MN3 are controlled by a precharge control signal ØBLP commonly input to a gate. The precharge control signal ØBLP has a 'low' logic state in the DRAM mode and an 'high' logic state in the standby mode. Therefore, in the standby mode, the sense amplifier driving bias signal signals RTO and / S lines are precharged to the precharge potential Vblp signal level, that is, to the inversion potential Vdd / 2.

However, in the case of the conventional semiconductor memory device, there is a problem of determining the overall operation speed by how fast the DRAM is charged or discharged with the sense amplifier driving bias signal RTO, / S as the integration and speed of the DRAM increases. In this case, the precharge circuit for precharging the conventional sense amplifier driving bias potential signal (RTO, / S) lines has increased power consumption due to the threshold voltage loss by using three NMOS as shown in FIG. In addition, the time taken when the RTO and / S signals are precharged to the inversion potential (Vdd / 2) becomes longer (as the slope becomes smoother) as shown in the simulation shown in FIG. Increasing the size of the transistor has a problem of increasing the layout area.

Accordingly, the present invention has been made to solve the above problems, an object of the present invention is to reduce the power consumption due to the loss of the threshold voltage, sense amplifier driving bias potential free that can perform a precharge operation quickly without increasing the layout To provide a charge circuit.

1 is a precharge circuit diagram for precharging a conventional sense amplifier driving bias potential.

2 is an operation timing diagram of FIG.

3 is a sense amplifier driving bias potential precharge circuit diagram according to an embodiment of the present invention.

4 is an operation timing diagram of FIG.

<Description of the symbols for the main parts of the drawings>

MN1 to MN5: N-channel MOS transistor

MP1 to MP2: P-channel MOS transistor

In order to achieve the above object, the sense amplifier driving bias potential precharge circuit of the present invention comprises a bit line sense amplifier for feedback sensing and amplifying the data of the cells carried on the pair of bit lines, the semiconductor memory device comprising: A pull-up bias signal line for supplying a potential potential, a pull-down bias signal line for supplying a ground potential to the sense amplifier, and the pull-up and pull-down bias signal lines when the memory device is in a standby state; A precharge signal line for transmitting a signal for precharging respectively, a pull-down device for transmitting a precharge potential signal to the pull-up bias signal line by the precharge signal, and a precharge signal by the precharge signal A pull-up element for transmitting a potential signal to the pull-down bias signal line, and the precharge signal And a transfer gate for equalizing the pull-up bias signal line and the pull-down bias signal line.

The pull-down device is an NMOS transistor, the pull-up device is a PMOS transistor, and the transfer gate is composed of NMOS and PMOS transistors whose source and drain are interconnected.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a sense amplifier driving bias potential precharge circuit diagram according to an embodiment of the present invention, a pull-up bias signal (RTO) line for supplying a power supply potential Vdd to a sense amplifier, and a ground potential ( Vss), a pre-charge signal for transmitting the pull-down bias signal (/ S) line and a signal (ØBLP) for precharging the pull-up and pull-down bias signal lines, respectively, when the memory device is in a standby state. A NMOS transistor MN5 for transmitting a precharge potential signal to the pull-up bias signal line by a signal line, the precharge signal ØBLP, and a precharge potential signal to the precharge signal ØBLP. PMOS transistor (MP2) to transmit to the pull-down bias signal line and the pre-charge signal (ØBLP) to equalize the pull-up bias signal line and pull-down bias signal line The transfer gates MP1 and MN4 are provided.

As can be seen from the above configuration, the present invention causes the size reduction by replacing the transfer gates MP1 and MN4 instead of the NMOS transistor MN1 of FIG. 1 and quickly equalizes the RTO and / S signals without a threshold voltage loss. equlize). That is, equalization is performed through the NMOS transistor MN4 which is a pull-down device of a transfer gate to pull down the pull-up bias signal line, and a transfer gate to pull-up the pull-down bias signal line. Since equalization is performed through the PMOS transistor MP1, which is a pull-up device, the equalization can be performed quickly without losing the threshold voltage caused by each device. In the prior art, an NMOS transistor MN1 of one terminal is used. Since the pull-up bias signal line and the pull-down bias signal line are equalized to prevent the circuit from failing by using a device having a large driving capability, in the present invention, the pull-up bias signal line and the pull-up bias signal line are equalized. We use a transfer gate that uses both pull-up and pull-down devices to equalize the pull-down bias signal line. The use of a device with a small driving capacity does not cause a problem, which may cause a size reduction. In addition, the NMOS transistor MN2 of FIG. 1 is replaced with a pull-down source MN5 so that when the RTO signal is sensed, the VMOS stays at Vdd and rapidly precharges (falls to Vdd / 2) without losing a threshold voltage. In addition, the MN3 of FIG. 1 was replaced with a pull-up source MP2 so that the / S signal was in Vss when sensing, and then quickly precharged (rising to Vdd / 2) without losing a threshold voltage. That is, in order to precharge the fly-up bias signal line and the pull-down bias signal line to the precharge potential voltage, both of the bias signal lines were precharged using the NMOS transistors MN2 and MN3. When the bias line is pulled down, the precharge can be quickly performed without losing the threshold voltage. On the other hand, when the pull-down bias line is pulled up, the threshold voltage is lost, and the circuit fails. In order to prevent), there is a problem in that a device having a very large driving capability must be used. Accordingly, in the present invention, the device for pulling up the pull-down bias signal line can be quickly precharged to the precharge potential voltage without loss of the threshold voltage by using the pull-up device PMOS transistor MP2.

When the word line WL is selected by the ras bar (/ RAS) signal and the data is loaded on the bit line pairs BL and / BL, the inverted potential Vdd / 2 is initially caused by the bias potential precharge signal ØBLP. The RTO and / S signals precharged by the &lt; RTI ID = 0.0 &gt;) &lt; / RTI &gt; are disabled by the bias potential precharge signal (ØBLP) and the sense amplifier pull-up bias signal (RTO) rises to the supply voltage (Vdd), The down signal / S falls to the ground voltage Vss. At this time, the minute difference data carried on the bit lines BL and / BL is sensed by the bit line sense amplifier and spread to the power supply voltage Vdd and the ground voltage Vss, respectively. Then, when the column address is selected, the data bus line pair ( DB, / DB) is loaded with data. When the sensing operation is completed, the RTO and / S signals are precharged to the inversion potential Vdd / 2 by the bias potential precharge signal ØBLP. 4 illustrates an operation waveform in which the RTO and / S signals are precharged. As can be seen from the simulation shown in FIG. 4, the present invention has a faster slope than the conventional sense amplifier driving bias potential precharge circuit, and thus can respond quickly for the next sensing operation.

As described above, according to the sense amplifier driving bias potential precharge circuit of the present invention, when precharging the sense amplifier driving bias potential during the standby operation of the DRAM, the power consumption due to the loss of the threshold voltage is reduced, and the precharge is quickly performed without increasing the layout. It has a very good effect of performing an action.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (3)

A semiconductor memory device comprising a bit line sense amplifier for feeding back and sensing and amplifying data of a cell carried on a pair of bit lines, the semiconductor memory device comprising: a pull-up bias signal line for supplying a power supply potential to the sense amplifier, and a ground potential to the sense amplifier; A precharge signal line for transmitting a signal for precharging the pull-up and pull-down bias signal lines, respectively, when the memory device is in a standby state, and the precharge signal; A pull-down element for transmitting a precharge potential signal to the pull-up bias signal line by a pull-up element, and a pull-up element for transmitting a precharge potential signal to the pull-down bias signal line by the precharge signal; Equalize the pull-up bias signal line and the pull-down bias signal line by the precharge signal; Passing Kate a sense amp drive bias potential precharge circuit, characterized in that comprising a. 2. The sense amplifier drive bias potential precharge circuit according to claim 1, wherein the pull-down element is an NMOS transistor and the pull-up element is a PMOS transistor. 2. The sense amplifier drive bias potential precharge circuit according to claim 1, wherein the transfer gate is composed of NMOS and PMOS transistors whose source and drain are interconnected.

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