KR960014176B1 - A locking device of a multi-signal processor system - Google Patents

Abstract

a lock processing signal generating counter(10) which generates a lock use signal and informs a processor of the timeout to finish the locking ; a buffer part(20) storing the processor name(ID) and the address of the processor performing the locking; and a system control part(30) cancelling the locking if the processor is abnormal or the timeout is generated, and informing the other processors.

Description

Locking device of multi-signal processing system

1 is a timing diagram showing an inter-lock reading order of TiCOM.

2 is a timing diagram showing the interlock write order of Tycom.

3 is a block diagram of a locking device of the multi-signal processing system according to the present invention.

* Explanation of symbols for main parts of the drawings

1,1 ': processor board 2: memory board

10,10 ': Lock processing signal generation counter 20: Buffer unit

30: system control unit 40: bus line

TECHNICAL FIELD The present invention relates to multiple signal processing systems, and in particular, a permanent-lock, in which the operation of a system or part thereof is effectively stopped by permanently continuing the occurrence of events that can never occur. It relates to a locking device of a multiple signal processing system to prevent the. Primarily in multi-signal processing systems, locking does not allow access simultaneously when multiple processors access a critical region of memory, until one particular processor starts and finishes work. A technology for continuously accessing processors one by one accessing the critical region to prevent other processors from accessing them.

There are three ways to implement this locking technique.

The first is to keep the locks consistent by occupying all the buses while one processor is locking the memory and not giving the buses the right of the other processors. The second is that the memory board itself is very functional so Consistency is maintained, and third, the processor locks a specific address in memory so that no other processor can lock the address until one processor's lock operation is complete.

Among the above methods, the first method reduces the efficiency of the entire system because the processor continues to occupy the system bus while performing the lock, and the second method is very complicated to implement the memory board. it's difficult. For this reason, the third method is often used as a locking method of a multi-signal processing system, for example, Tycom.

In the Tycom system, the lock is performed without occupying the bus in the RMW cycle of the processor. For this purpose, the memory area used in Tycom's RMW cycle is limited to 1 byte, 2 bytes, 4 bytes, etc. so that only that area is allowed to prevent access to other processors while one processor is running. It is.

In order to perform this function, the transfer type provided by the bus is pipeline type, and the inter-lock read order is as shown in FIG. 1, and the inter-lock write The order is as shown in FIG. 2, where the read period of the RMW corresponds to the interlock read period, and the write period of the RMW corresponds to the interlock write period.

The operation on the bus of the interlock read is the same as the operation of the general read, and serves to inform that the currently accessed area is part of the RMW cycle, and the memory controller receiving the interlock read prevents access to another processor. The processor that reads data by the interlock read performs internal operations, and then writes data to the area again using interlock write, and the operation on the interlock write bus is the same as that of a normal write operation. The memory controller writes data to the area and then releases the lock bound by the interlock write.

The interlock reading and writing order will be described in more detail as follows. When reading an interlock, the selected processor outputs a signal according to a data acquisition request and a request acquisition to a memory, drives an address bus, and then searches a cache tag. In the memory, the address bus is latched and decoded to drive an address acknowledgment signal, thereby reading data accessed by a processor that latches the address acknowledgment signal of the memory.

On the other hand, during interlock writing, if the selected processor outputs a signal corresponding to a data transmission request and acquisition to the memory and then drives the address bus and the data bus, the address bus and the data bus are latched in the memory. When outputting a signal according to data recognition, the processor latches a signal according to address and data recognition. This method has the advantage of reducing the efficiency of the system caused by continuously occupying the system bus while the processor performs the lock, but eliminating the need for complicated memory board implementation, but the specific processor performs the lock operation by interlocking. After that, normal interlock write may not occur due to the abnormality of the processor board itself, or interlock write may not be performed properly on the bus or the memory board even if the interlock write is performed on the processor board. In addition, when a plurality of processors attempt to simultaneously lock the same address, if the processor that performs the first interlock read has the lowest priority, it is locked by repeated interlock reads performed by other processors having higher priority. Do write First, follow the first interlock read rankings are not the lowest processor to extract the bundled lock because you can not use the bus, there is a problem that the fall in permanent locked.

Accordingly, an object of the present invention is to provide a locking device of a multiple signal processing system that can solve the above problems and prevent the occurrence of a permanent lock state.

Locking device of the present invention for achieving the above object, the lock processing signal generation counter for informing the lock is performed and the end of the lock, the buffer unit for storing the processor name and address of the processor in the lock and the processor is performing the lock normally If it does not operate, it is characterized in that it is provided with a system control unit to notify the other processors directly after unlocking.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a view illustrating a locking device of a multi-signal processing system according to the present invention. When a predetermined processor is performing lock operation, a lock busy signal is generated so that other processors do not perform a lock operation. A plurality of processor boards (1, 1 ') each having a lock processing signal generation counter (10) informing the processor to time out so as to end the lock, and a buffer unit (20) for storing the processor name and address of the processor under lock And a memory board 2 connected to the lock processing signal generation counter 10 and a bus line 40 to transmit a signal, and a processor board 1, 1 'and a memory board 2 and a bus. Check the processor name and address stored in the buffer unit 20 connected to the line, and the lock is being released even if the processor being locked is abnormal or the timeout signal is generated. If you do not unscrew the lock consists of a direct system control unit 30 notifying the other processors, the operation is as follows. Once the lock is performed by one specific processor, the lock processing signal generation counter 10 notifies the other processor that the lock is being performed, and if the lock processing signal is repeatedly received for a predetermined time, the lock processing signal time-out is performed. timeout).

When the processor recognizes the timeout, the processor stops the current cycle once and interrupts the system controller 30 to notify the timeout. The system controller 30 accordingly processes the memory board 1,1 '. Check the occupied address and the processor name (ID: IDentification) of the processor that is performing the lock and check if it is working normally by interrupting the processor. Wait for a while and access the memory to see if the lock is released.

However, if the processor does not operate normally or the lock is not released after a certain period of time, the system controller 30 directly interlocks the write to release the lock and interrupts each processor to inform that the lock is released. Continue the operation.

Accordingly, the present invention prevents another processor from performing a lock operation until the processor locks a specific address of the memory until the lock operation of the processor is completed, and the state of the processor, memory, or bus is not good or an operation error occurs. By preventing the permanent locking state that may occur due to the, it is possible to improve the signal processing efficiency of the entire system.

Claims (1)

A lock processing signal generation counter 10 which generates a lock busy signal so that other processors do not perform a lock operation when the predetermined processor is in lock operation, and notifies the processor that the lock is being terminated after a predetermined time elapses. The processor 20 stores a processor name (ID) and an address of the processor (1) under lock, and checks the processor name and address stored in the buffer unit (20). Locking device of the multi-signal processing system, characterized in that it is provided with a system control unit (30) to notify the other processors after the direct unlock if the lock is not released even after the occurrence.