KR960013975B1 - Memory for tdx-10 - Google Patents

Abstract

The circuit includes a bus control/memory unit(40) for allotting an address bus and a data bus to an upper controller(20), a lower controller(30) and acoustic signal generator(60) and for performing input/output of information of the above units(20,30,60). The bus control/memory(40) includes an address bus control unit(80), data bus control unit(70), the first buffer(81), the second buffer(82), the third buffer(83), the first latch(71), the second latch(72), and the third latch(73).

Description

[Name of invention]

Memory I / O Circuit of Electronic Switching System Signaling Service Device and Its Method

[Brief Description of Drawings]

1 is a configuration diagram of a memory input / output circuit of a conventional signal service device.

2 is a configuration diagram of a memory input / output circuit of a signal service device according to the present invention.

3 is a detailed block diagram of the bus control / memory unit shown in FIG.

* Explanation of symbols for main parts of the drawings

10,30: lower control unit 11: dual port memory unit

12,20: upper control unit 13: memory unit

14,60: sound signal transmitter 15,50: sound signal detector

40: bus control / memory section 70: data control section

71 to 73: latch 80: address control unit

81-83: Buffer 90: Memory

Detailed description of the invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal service device of an all-electronic switching system. In particular, the all-electronic switching system signal service is provided so that a plurality of circuits share one common memory in common, thereby reducing the number of memories and improving circuit density and economy. A memory input circuit of a device and a method thereof are provided.

As shown in FIG. 1, the memory input / output circuit of the conventional electronic switching system signal service device includes a lower control unit 10, a dual port memory unit 11, an upper control unit 12, a memory unit 13, and a signal sound transmitting unit. 14 and a signal sound detecting unit 15 are provided. The upper control unit 12 records the control information in the dual port memory unit 11 through the TD bus matching port, reads the beep detection information and the signal transmission information recorded in the dual port memory unit 11, and outputs a multi-frequency signal. Analyze The lower control unit 10 reads out the control information recorded in the dual port memory unit 11 through the main control port and outputs the signal sound detection information of the signal sound detection unit 15 when it is output to the signal sound detection unit 15 and the memory unit 13. The data is read and recorded in the dual port memory section 11. The beep detection unit 5 operates according to the control information supplied from the lower control unit 10 and detects the beep sound supplied from the outside and outputs the beep detection information to the lower control unit 10. The signal transmission unit 14 generates a signal sound according to the control information stored in the memory unit 13 and outputs it to the outside.

As described above, in the conventional signal service apparatus, an expensive dual port memory unit 11 is used for communication between the lower control unit 10 and the upper control unit 12, and a separate signal transmission control for the signal transmission unit 14 is performed. Since the memory unit 13 is used, there is a problem in that economical efficiency and circuit integration are reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and the memory input / output circuit of the all-electronic switching system signal service device for improving the economics and the circuit integration by allowing a plurality of circuit units to use one common memory in common. And a method thereof.

In order to achieve the above object, the present invention allocates an address bus and a data bus to an upper control unit, a lower control unit, and a beep transmitting unit, thereby providing a bus control / memory unit for inputting and outputting information to the upper control unit, the lower control unit, and a beep transmitting unit. A memory input / output circuit of an all-electronic switching system signal service device is provided.

In addition, the present invention is a first process of the upper control unit, the lower control unit and the beep transmitting unit individually request access to input and output information to the memory; A second process of allocating an address bus to the upper control unit, the lower control unit, the lower control unit, and the beep transmitting unit that requested access; Enabling the memory to perform an information input / output operation; And a fourth process of allocating a data bus to the control unit, the lower control unit, and the beep transmitting unit requesting an access request.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is an upper control unit 20, a lower control unit 30, a bus control / memory unit 40, a signal sound detection unit 50 and a signal sound as shown in FIG. 2 of the memory service input and output of the signal service apparatus according to the present invention. It is provided with the sending part 60. The upper control unit 20 records control information in the memory unit 40 through the TD bus matching port, and reads beep detection information and beep transmission information recorded in the bus control / memory unit 40 through the TD bus port. Analyze the frequency signal. The lower control section 30 reads out the control information recorded in the bus control / memory section 40 through the main port and outputs the signal to the beep detection section 50, and reads the beep detection information of the beep detection section 50 to control the bus. Write to memory 40. The signal transmission unit 60 reads out the control information recorded in the bus control / memory unit 40 through the signal transmission port and transmits the signal sound to the outside. The bus control / memory unit 40 records and outputs information by allocating address buses and data buses of the memory provided to the upper control unit 20, the lower control unit 30, and the signal sound transmitting unit 60.

The bus control / memory section 40 comprises a data bus control section 70, an address bus control section 80 and a memory 90 as shown in FIG. The data bus control unit 70 includes latches 71 to 73, and the address bus control unit 80 includes buffers 81 to 83. The latch 71 receives information input and output between the main control port data bus on the lower controller 30 side and the data bus on the memory 90 side according to the control signal C1 supplied from the memory controller (not shown). By assigning the data bus on the memory 90 side to the main control port data bus, the latch 72 controls the upper control unit 20 to the TD bus matching port data bus on the upper control unit 20 side and the memory 90 side. The data bus on the memory 90 side is allocated to the TD bus matching port data bus by transferring information input / output between the data buses according to the control signal C2 supplied from the memory controller, and the latch 73 transmits the signal sound transmission unit 90. Signal transmission port data bus by transmitting the information input / output between the data transmission port data bus and the memory 90 side according to the control signal C3 supplied from the memory controller The memory allocated to data bus 90 side. The buffer 81 transfers the address supplied from the main control port address bus on the lower control unit 30 side to the main control port address on the memory 90 side in accordance with the control signal C4 of the memory control unit. The address bus on the () side, and the buffer 82 receives the address supplied from the TD bus matching port address bus on the upper control unit 20 side according to the control signal C5 of the memory control unit. The bus is allocated an address bus on the memory 90 side to the TD bus matching port address bus, and the buffer 83 receives an address supplied from the signal sending port address bus on the beep transmitting unit 60 side. The memory bus 90 address bus is allocated to the signal sending port address bus by transferring the address bus to the memory 90 side according to the control signal C6. . When the memory select enable signal C7 is supplied from the memory control unit, the memory 90 is addressed according to the address supplied through the address bus control unit 80 to output the information recorded therein to the data bus control unit 70. When the memory select enable signal C7 and the write enable signal C8 are supplied from the memory control unit, the address information is addressed according to the address supplied through the address bus control unit 80 to receive information supplied from the bus control unit 70. Record it.

When the control unit 20, the lower control unit 30, and the beeper transmitting unit 60 each request the memory control unit to access the memory 90 individually to read the information recorded in the memory 90, The control unit controls the address bus control unit 80 using the control signals C4 to C6 so that the address of the corresponding circuit unit requested for access is transmitted to the memory 90, and the memory select enable signal C7 to the memory 90 side. ) To enable the memory 90 and to output the control signals C1 to C3 to the data bus control unit 70 to control the data bus control unit 70 so that information is transferred to the corresponding circuit unit requesting access. As a result, the information output from the memory 90 is transferred to the corresponding circuit portion that has requested access through the data bus controller 70.

When the control unit 20, the lower control unit 30, and the beeper transmitting unit 60 respectively request the memory control unit to access the memory 90 to record information in the memory 90, the memory control unit The address bus controller 80 is controlled using the control signals C4 to C6 so that the address of the corresponding circuit portion requested for access is transferred to the memory 90, and the memory selection enable signal C7 is written to the memory 90 side. The enable signal C8 is output to enable the memory 90. The control signal C1 to C3 is output to the data bus control unit 70 so that information from the corresponding circuit unit that has requested access is stored in the memory 90. The data bus controller 70 is controlled to be transferred. Accordingly, the memory 90 records information supplied through the data bus controller 70 from the corresponding circuit portion that has requested access.

In addition, when the upper control unit 20, the lower control unit 30, and the beep transmitting unit 60 simultaneously request access to the memory control unit to record or read information to the memory 90, the memory control unit stores the memory according to the priority. The address bus and data bus on the 90 side are allocated to the circuit section. The address bus and data bus of the memory 90 side are assigned to the main port port bus and the main port data bus, and then the address of the memory 90 side is assigned to the TD bus matching port address bus and the TD bus matching port data bus. The bus and data bus are allocated, and then the signal sending port address bus and the signal sending port data buses are allocated the address bus and data bus on the memory 90 side. In this way, the address bus and the data bus on the memory 90 side are allocated in accordance with the priority to prevent collision of the input / output information.

As described above, in the present invention, since a plurality of circuit units share one general memory in common, economics and circuit integration can be improved.

Claims (6)

In the memory I / O circuit of the all-electronic switching system signal service device, the upper control unit 20 and the lower control unit are allocated to the upper control unit 20, the lower control unit 30, and the signal transmission unit 60 by assigning an address bus and a data bus. (30) and a bus control / memory section (40) for inputting and outputting information to and from the signal transmission unit (60). The address bus control unit of claim 1, wherein the bus control / memory unit 40 allocates an address bus to the upper control unit 20, the lower control unit 30, and the signal transmission unit 60 under the control of the memory control unit. 80; And an electronic data exchange control unit (70) for allocating a data bus to the upper control unit (20), the lower control unit (30), and the signal transmission unit (60) under the control of the memory control unit. Memory input / output circuit of signal service device. 3. The memory controller of claim 2, wherein the address controller 80 is configured to allocate the address bus to the lower controller 30 in response to a control signal C4 supplied from the memory controller. A second butter 82 for allocating an address bus to the upper control unit 20 according to the control signal C5 supplied from the control unit C5 and the signal sound transmitting unit 60 according to the control signal C6 supplied from the memory control unit. And a third buffer (83) for allocating an address bus to the side. The first latch 71 and the memory controller of claim 2, wherein the data bus controller 70 allocates a data bus to the lower controller 30 according to a control signal C1 supplied from the memory controller. A second latch 72 for allocating a data bus to the upper control unit 20 according to the control signal C2 supplied from the controller, and the signal sound transmitting unit according to the control signal C3 supplied from the memory control unit. And a third latch (73) for allocating a data bus to the (60) side. In the memory input / output method of the all-electronic switching system signal service device, the upper control unit 20, the lower control unit 30, and the signal transmission unit 60 each separately request for access to input and output information to the memory 90. 1 course; A second process of allocating an address bus to the upper control unit 20, the lower control unit 30, and the signal transmission unit 60 which have requested access; A third step of enabling the memory (90) to perform an information input / output operation; And a fourth process of allocating a data bus to the upper control unit (20), the lower control unit (30), and the signal transmission unit (60) that requested access. 6. The method of claim 5, wherein, in the first process, when the upper control unit 20, the lower control unit 30, and the signal transmission unit 60 simultaneously request access to input and output information to the memory 90, a predetermined priority is given. And allocating the address bus and the data bus to the upper control part (20), the lower control part (30) and the beep transmitting part (60).