KR960013780B1 - Semiconductor device and the manufacturing method of device isolation - Google Patents

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Description

Device Separation Semiconductor Device and Manufacturing Method Thereof

1 is a cross-sectional view showing the configuration of a semiconductor device according to the present invention.

2 is a cross-sectional view showing another configuration of the device for separating semiconductor devices according to the present invention.

Figure 3 (a) is a schematic diagram for explaining the separation threshold.

3 (b) is a graph showing the relationship between voltage and current.

Figure 4 (a) is a schematic diagram for explaining the breakdown voltage.

4 (b) is a graph showing the relationship between voltage and current.

5 is a diagram for comparing (a) the LOCOS structure, (b) the conventional structure, and (c) the separation threshold of this embodiment.

Figure 6 is a diagram for comparing the breakdown voltage (a) LOCOS structure, (b) conventional structure, (c) in the examples.

7 is a graph in which the etch rate for silicon sets the mixing ratio of etching reagents such as the etch rate for resist.

8 to 18 are cross-sectional views sequentially showing a method for manufacturing a semiconductor device according to the present invention for each step.

19 is a graph showing the concentration distribution in a substrate when boron is injected into the substrate at a predetermined energy and concentration.

20 to 34 are cross-sectional views sequentially showing a method of manufacturing a CMOS transistor according to the present invention for each step.

35 is a sectional view of a conventional semiconductor device.

36 to 40 are cross-sectional views sequentially showing a conventional method for manufacturing a semiconductor device for each step.

41 to 52 are cross-sectional views sequentially showing a conventional method for manufacturing a CMOS transistor for each step.

Fig. 53 is a schematic diagram showing the diffusion of impurities during heat treatment in the structure of a conventional semiconductor device.

54 is a schematic diagram showing an increase in concentration due to overlapping impurity diffusion regions in a conventional semiconductor device structure of narrow channels.

* Explanation of symbols for main parts of the drawings

1,13: semiconductor substrate 2,4,11,12,14,16,23: oxide film

3,15,21: semiconductor layer 5,17,22,24,25,27,91: resist mask

6,8,10: Groove 8a: Impurity Diffusion Area

1a, 35 p-type impurity region 26 n-type impurity region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for device isolation and a method for manufacturing the same, and more particularly, to a configuration of a MOS transistor having a device isolation structure and a method for manufacturing the same.

The isolation region structure of a semiconductor device in which a plurality of MOS transistors are formed on one substrate is disclosed in Japanese Patent Laid-Open No. 63-170927.

The isolation region structure disclosed in this publication is described below with reference to FIG.

In the separation structure of the semiconductor device, the groove 31 is formed at a depth of about 1 to 2 탆 from the surface of the p-type semiconductor substrate 30. A p ⁺ type diffusion layer 36 of 10 to 10 cm is formed to serve as a channel stopper. In addition, the p ⁺ type diffusion layer 36 also plays a role of preventing punch through phenomenon. On the other hand, an oxide film 38 is formed on the upper surface of the p ⁺ semiconductor layer 35 to a thickness of about 1000 to 2000 micrometers, and the gate oxide film 39 is formed on the surface of the p-type semiconductor substrate 30 other than the region where the oxide film 38 is formed. Is formed. The following describes the structure of the MOS transistor with the isolation structure.

The gate electrode 40 is formed on the gate oxide film 39 of the above-described isolation structure.

Source / drain regions 41 of n ⁺ type impurity regions are formed at predetermined depths on both sides of the gate electrode 40. The gate station 40 extends below the interlayer insulating layer 42 above the groove 31.

Next, a manufacturing method of the separation structure will be described with reference to FIGS. 36 to 40. FIG.

In FIG. 36, a thin thermal oxide film 32 having a thickness of about 300 microseconds is formed on the p-type semiconductor substrate 30, and the nitrogen film 33 is etched by the CVD method to etch a groove 31 having a depth of about 1 to 2 탆. To form.

In FIG. 37, the thermal oxide film 43 is formed relatively thick on the sidewalls of the groove 31, and then the thermal oxide film 34 at the bottom of the groove 31 is removed by anisotropic etching to expose the semiconductor substrate 30.

At this time, since the transistor formation region is covered with the nitrogen film 33 serving as a mask, it is not etched.

Thereafter, the polysilicon 35 is grown to about 1 to 2 km on the front surface of the substrate including the groove 31.

Next, in FIG. 38, a p-conducting impurity such as a substrate is diffused by heat treatment to a depth reaching the polycrystalline silicon 35 by ion implantation or vapor phase doping.

In this way, a p + type diffusion layer 36 is formed in the semiconductor substrate 30 under the bottom of the groove 31 as a channel stopper. At this time, since the transistor formation region is covered with the nitrogen film 33, impurities do not diffuse into this region. Moreover, since the side surface of the groove | channel 31 is coat | covered with the thermal oxidation film 34, water impurities do not diffuse here.

Thereafter, a photoresist film 37 is formed on the semiconductor substrate in order to make the surface of the polysilicon 35 uniform. Next, the photoresist film 37 and the polysilicon 35 in which the impurities are diffused are removed by anisotropic etching until the surface of the nitrogen film 33 is exposed.

Thus, as shown in FIG. 39, the structure which filled the polysilicon 35 in the groove | channel 31 is completed. Thereafter, the semiconductor substrate 30 is thermally oxidized to form a relatively thin oxide film 38 having a thickness of about 1000 GPa to 2000 GPa on the surface of the polysilicon filled in the groove 31.

Next, the nitrogen oxide film 33 and the thermal oxide film 32 are removed to form a gate oxide film 39 (FIG. 40).

The separation structure is thus completed.

Next, after the isolation structure shown in FIG. 40 is formed, the gate electrode 40 is patterned into a predetermined shape to form the source / drain region 41.

Thereafter, the interlayer insulating film 42 is grown to drill a contact hole at a predetermined position, and the metal wiring 43 is formed.

In this way, the MOS transistor shown in FIG. 35 is completed.

Next, a method of manufacturing a CMOS transistor using an element isolation structure of a semiconductor device will be described with reference to FIGS. 41 to 52. FIG. In FIG. 41, the surface of the right half of the p-type semiconductor substrate 5 is coated with a resist film 52, and phosphorus (P) is 500KeV-1.5MeV in a condition of 1 × 10 ^{12 to} 1 × 10 ¹⁵ cm ^-2 . The n-type impurity diffusion region 3 is then formed by implanting a predetermined depth in the region on the left half of the p-type semiconductor substrate 51 at a temperature of 800 to 1200 캜 for 20 minutes to 10 hours.

Next, after removing the resist film 52 in FIG. 42, the surface of the n-type impurity diffusion region 53 of the p-type semiconductor substrate 51 is covered with the resist film 54. Next, as shown in FIG.

Subsequently, boron (B) is injected into the region of the right half of the p-type semiconductor substrate 51 at 200 × eV −1 MeV under the conditions of 1 × 10 ^{12 to} 1 × 10 ¹⁵ cm ^-2 and 20 minutes to a temperature of 800 to 1200 ° C. The p-type impurity diffusion region 55 is formed by heat treatment for 10 hours. Next, in FIG. 43, after removing the resist film 54, a thin oxide film 56 having a thickness of about 300 microseconds is formed on the surfaces of the n-type impurity diffusion region 53 and the p-type impurity diffusion region 55, followed by CVD. The nitrogen film 57 is grown on the oxide film 56 using the method.

Thereafter, the resist film 58 is applied and patterned on the nitrogen film 57.

Using the zelist film 58 as a mask, the nitrogen film 57, the oxygen film 56, the n-type impurity diffusion region 53 and the p-type impurity diffusion region 55, which are to be device isolation regions, are about 1 to 2 mu m. The grooves 59 and 60 are formed as shown in FIG. 44 by etching to the depth of. Next, in FIG. 45, after removing the resist film 58, the thermal oxide films 61 and 62 are formed relatively thick inside the grooves 59 and 60, and then the bottom surface of the grooves 59 and 60 are removed. The thermal oxide films 61 and 62 are removed by anisotropic etching and the semiconductor substrate 51 is exposed.

At this time, since the n-type impurity diffusion region 53 and the p-type impurity diffusion region 55 are covered with the nitrogen film 57 serving as a mask, they are not etched.

Thereafter, as shown in FIG. 46, the polysilicon 70 is grown to about 1 to 2 mu m on the entire surface of the semiconductor substrate 51 including the grooves 59 and 60. As shown in FIG. Next, in FIG. 47, the region of the surface of the polysilicon 70 above the p-type impurity diffusion region 55 is again covered with a resist film 63, and then the polycrystalline silicon above the n-type impurity diffusion region 53 is next. Phosphorus (P) is injected into 70 at 100 KeV under 1 × 10 ^{12 to} 1 × 10 ¹⁶ cm ^-2 .

Next, after removing the resist film 63, a resist film 64 is formed on the upper surface of the high concentration n + type impurity diffusion region 70a as shown in FIG.

In the same manner as described above, boron (B) is injected into the polycrystalline silicon 70 above the p-type impurity diffusion region 55 at 500 x KeV under the conditions of 1 × 10 ^{12 to} 1 × 10 ¹⁵ cm ^-2 .

After removing the resist film 64, the photoresist film 65 is applied to the surfaces of the n ⁺ type impurity diffusion region 70a and the p ⁺ type impurity diffusion region 70b as shown in FIG. Equalize.

Then, in FIG. 50, the photoresist film 65, the n ⁺ type impurity diffusion region 70a and the p ⁺ type impurity diffusion region 70b are removed by etching to expose the nitrogen film 57, and the temperature is 800 to 800. The heat treatment is performed for 20 minutes to 10 hours under the condition of 1200 占 폚 so that impurities in the n ⁺ type impurity diffusion region 70a and the p ⁺ type impurity diffusion region 70b are respectively removed from the bottoms of the grooves 59 and 60. To spread.

As a result, the n ₊ -type impurity diffusion region 70a and the p ₊ -type impurity diffusion region 70b are respectively filled in the grooves 59 and 60, and the n ₊ diffusion layer 53 serving as a channel stopper at the bottom of these grooves. And p ₊ diffusion layer 55 is formed. In FIG. 51, a relatively thin oxide film is formed on the surfaces of the n ₊ type impurity diffusion region 70a and the p ₊ type impurity diffusion region 70b in which the semiconductor substrate 51 is thermally oxidized and filled in the grooves 59 and 60. (66) (67) (about 1000-2000 micrometers) are formed. Thereafter, the nitrogen film 57 and the thermal oxide film 56 are removed, and then a gate oxide film 68 is formed. In this way, the separation structure used for the CMOS is completed.

Thereafter, the gate oxide film 80 is deposited to form the gate electrode 81, and the gate electrode 81 is etched into a predetermined shape by photolithography.

Thereafter, source / drain regions 82 and 83 are formed in the substrate, respectively.

The interlayer oxide film 84 is then deposited on the entire surface on the substrate, and the contact holes 85 reaching the source / drain regions 82 and 83 are opened by the photolithography technique.

Aluminum 86 is deposited by sputtering, and the aluminum 86 is etched using photolithography to complete a CMOS transistor as shown in FIG.

However, the structure of the semiconductor device has the following problems.

First, as shown in FIG. 53, in the heat treatment necessary for forming the channel stopper region formed at the bottom of the groove, the impurity concentration is high, such as 10 ²⁰ to 10 ²² cm 3, so that impurities diffuse into the substrate extensively and the surface of the substrate As the impurity concentration in the vicinity rises, the threshold voltage rises.

As shown in Fig. 54 (a) and (b), when the separation width is narrow, the impurities from the upper separation region overlap each other, whereby the concentration tends to rise, and this phenomenon is more remarkable in the narrow channel.

In addition, since the atomic radius of silicon and boron is different, defects are likely to occur in the substrate, thereby causing leakage current.

Second, when the semiconductor device structure is used as a CMOS structure, the number of manufacturing processes becomes extremely large and reliability must be secured in each process. Therefore, the reliability of the product, the cost reduction and the improvement of productivity are prevented. One object of the present invention is to provide a device separation semiconductor device having a separation structure in the shape of a groove that does not require a channel stopper region.

Another object of the present invention is to provide a method of fabricating a semiconductor device for device isolation, in which an impurity is injected into a substrate so that a region of maximum impurity concentration is located at a predetermined depth of the substrate.

In order to achieve the above object, the element isolation semiconductor device according to the first invention of the present invention has a maximum impurity concentration band of the first conductive type impurity approximately parallel to the main surface over a predetermined depth from the main surface. The semiconductor substrate also has a low impurity concentration between the main surface and the maximum impurity concentration band.

The separation groove has sidewalls extending from the main surface to the maximum impurity concentration band, and the separation groove is filled with the separation material. In this device isolation semiconductor device, since a uniform p ₊ high concentration region is formed substantially at the bottom of the isolation region, it does not affect the separation threshold value, and the source is maintained by a uniform p ₊ high concentration region even in the breakdown voltage, that is, punch-through resistance. The punch-through phenomenon can be effectively suppressed without being bonded to the depletion layer from the / drain region.

The semiconductor device for device isolation according to the second aspect of the present invention is a semiconductor substrate having a first conductive impurity region having a maximum impurity concentration at a predetermined depth in a depth direction from a surface thereof, and a surface of a semiconductor substrate. A groove formed at a predetermined depth in the impurity region of the first conductive type, and spaced apart from the sidewalls in the groove, and only a bottom thereof contacts the first conductive type impurity region of the semiconductor substrate, An impurity diffusion region having an impurity concentration almost equal to that of the impurity region, and an oxide film covering the upper surface of the impurity diffusion region and the surface of the semiconductor substrate and filling the gap between the inner side wall of the groove and the impurity diffusion region.

According to the element isolation semiconductor device, first, an oxide film is formed in the sidewall portion of the groove as a separation material provided in the groove. A semiconductor layer is provided in the oxide film formed on the sidewall of the groove.

In this way, the difference in thermal expansion coefficient between the separation material and the semiconductor substrate can be eliminated.

This prevents the occurrence of cracks in the separation material and, therefore, prevents the occurrence of leak current.

In addition, since the high impurity region of p ₊ is formed substantially substantially uniformly at the bottom of the separation region, the separation threshold is not affected. In addition, even with respect to the breakdown voltage, that is, punchthrough resistance, the depletion layer from the source / drain region does not extend due to the high impurity region of p ₊ , and thus punchthrough can be effectively suppressed.

In order to achieve the above-described invention, according to the method for manufacturing a device for semiconductor device separation according to the first aspect of the present invention, grooves are formed at a predetermined depth on the main surface of the semiconductor substrate.

A separation material is formed in this groove. Impurities are introduced such that the maximum impurity concentration band is at a predetermined depth approximately parallel to the main surface. There is a low impurity concentration between the maximum impurity concentration band and the main surface, and the groove depth extends to the maximum impurity concentration band.

According to a second aspect of the present invention, there is provided a method of fabricating a semiconductor device for device isolation, comprising the steps of: forming a groove having a predetermined depth in a semiconductor substrate; and forming an oxide film in an inner film except for the bottom of the groove; And depositing a semiconductor layer in the groove and implanting and diffusing impurities of the first conductivity type to the bottom depth of the groove to the semiconductor substrate and the semiconductor layer.

According to this manufacturing method, the number of impurity implantation steps can be reduced, thereby reducing the number of steps for forming a resist film. Therefore, the manufacturing process of the semiconductor device can be reduced.

Next, a semiconductor device and a manufacturing method according to the present invention will be described with reference to FIGS.

In FIG. 1, the structure of a semiconductor device is a semiconductor substrate having a p-type impurity region la of the first conductivity type in which the concentration of the impurity region is maximized from the surface, for example, at a depth of 1.7 µm or 2.8 µm or 4.0 µm. 1) and a groove 6 formed from the surface of the p-type impurity region la of the semiconductor substrate 1 over a depth of about 0.3 to 1.0 mu m in the p-type impurity region la.

The inside of the groove 6 is spaced apart from the inner side wall, and only the bottom surface of the groove 6 is in contact with the semiconductor substrate 1, and the impurity region la has the same concentration as the p-type impurity diffusion region 8a and the groove. It is composed of an oxide film 11 which fills the space between the inner side wall of (6) and the p-type impurity diffusion region 8a and covers the upper surface of the impurity diffusion region 8a and the surface of the semiconductor substrate 1.

2, another configuration will be described. In this configuration, the inside of the groove 6 is entirely filled with an oxide film. However, in this configuration, since the thermal expansion coefficient difference between the semiconductor substrate 1 and the oxide film 11 is large, cracks occur in the oxide film during the heat treatment process.

If a crack occurs in the oxide film, a leakage current is generated in the semiconductor substrate, thereby degrading device isolation capability.

Therefore, as shown in FIG. 1, it is preferable to provide a semiconductor layer in the groove to eliminate thermal expansion coefficient aberration. The following describes the configuration of FIG.

The gate electrode 7 is formed on the upper surface of the oxide film 11 in the region where the transistor is formed, and the source / drain regions 9 and 10 of the n ₊ type impurity region are formed in both impurity regions la of the gate electrode 7. ) Is formed at a predetermined depth.

The following describes the separability. As regards separability, the “separation threshold” and “separation pressure” should be considered. In Fig. 3 (a) and (b), the separation threshold value is determined by monitoring the current I _d to determine the conduction of the left and right source / drain regions 100 and 101 when the gate voltage is set to V. FIG.

In Fig. 4 (a) and (b), the breakdown voltage is determined by how much V is applied to one source / drain region 100 and 101, and adjacent source / drain regions 100 and 101 conduct or bond fracture. The relationship between the voltage V _d and the current I _d is indicated. The separation threshold of the LOCOS structure, the conventional structure and the structure of this embodiment is compared with the "separation threshold" DHK "separate withstand voltage". When comparing the respective “separated thresholds”, the path L between the elements 100 and 101 is short in the LOCOS structure with reference to FIGS. 5A, 5B, and 5C. It turns out that it is easy to conduct because the area of the X mark is likely to be reversed.

In the conventional structure, the path between the elements 100 and 101 is long, and the region of the X table in the groove side wall portion drawing does not easily conduct because inversion does not occur.

In addition, in the structure of this embodiment, the path between the elements 100 and 101 is long as in the conventional structure, and does not invert easily in the X-marked area in the drawing of the side wall of the groove, so that it is not easily conducted.

In addition, since the high concentration p ₊ layer 103 is formed at the bottom of the groove, even if the inversion layer is formed, the conduction is impossible, so that the separation ability can be sufficiently improved.

Next, when comparing “separation breakdown voltage”, in the LOCOS structure, the path L between the elements 100 and 101 is short as described above, referring to FIG. 6 (a) (b) (c). This is easy to occur.

In the conventional structure, since there is only one high concentration layer 102, there is a possibility that the depletion layer is conducted in the deep portion of the substrate, causing punch-through phenomenon.

However, in the structure of this embodiment, the p ₊ layer 103 can be substantially formed at the bottom of the substrate by selecting impurity injection energy to achieve the maximum impurity concentration at the bottom of the groove.

As a result, the depletion layer from the source / drain region must cross the p ₊ layer 110 in order to conduct, so that the punch-through phenomenon can be effectively suppressed.

By using the above structure for the nMOS transistor, device isolation can be performed without providing a channel stopper region at the bottom of the isolation region.

In the method for manufacturing a semiconductor device having the above structure, referring to FIG. 8, a first oxide film ₂ of SIO ₂ is formed on the surface of the semiconductor substrate 1 by a thickness of about 300 kV using a thermal oxidation method.

The first semiconductor layer 3 made of polysilicon was formed on the surface of the first oxide film 2 using a CVD method to a thickness of about 500 to 2000 GPa, and then heat was formed on the surface of the first semiconductor layer 3. By using the oxidation method, the second oxide film 4 of SIO ₂ is formed to a thickness of about 300 GPa.

In FIG. 9, a resist pattern 5 of a predetermined pattern is formed on the surface of the second oxide film 4, and the groove 6 having a depth of about 0.3 to 1.0 mu m is formed using the resist film 5 as a mask as shown in FIG. ) Is formed by anisotropic etching. After the groove 6 is formed, the resist film 5 is removed in FIG. 11, and an oxide film is formed on the inner surface of the groove 6 by thermal oxidation. At this time, the first semiconductor layer 3 is further oxidized and the second oxide film 4 is thickened. The second oxide film 4 and the first oxide film 2 are integrated at the side surface of the groove 6.

The oxide film thus formed is hereinafter referred to as oxide film 11.

Next, in FIG. 12, the semiconductor substrate 1 is exposed by anisotropic etching the oxide film 11 on the bottom of the groove 6. Then, in FIG. 13, the growth temperature using the gas such as SICL ₄ , SIHCL ₃ , SIH ₂ CL ₂ , SIH ₄ by epitaxial growth on the inside of the groove 6 and on the surface of the oxide film 11. The second semiconductor layer 8 is formed with a growth rate of 0.2 to 1.4 mu m / min in the range of about 700 deg.

14 and 15, in order to make the surface of the semiconductor layer 8 uniform, a resist film 91 is formed flat on the surface of the semiconductor layer 8 and etched to a predetermined depth.

This etching is performed by adding the etch rate for silicon and the resist for the mixed gas of CCL ₄ and O ₂ to silicon as shown in FIG.

In FIG. 16, the semiconductor layer 8 is thermally oxidized deeper than the surface of the semiconductor substrate 1 to form the oxide film 12. In FIG. The oxide film 11 and the oxide film 12 are etched until the surface of the semiconductor layer 3 is exposed.

Thereafter, only the exposed semiconductor layer 3 is removed by etching as shown in FIG.

Next, in FIG. 18, the semiconductor substrate 1 and the first conductive type impurity, for example, boron (B), have a constant energy value within the range of 200 KeV to 1MeV 1 × 10 ^{12 to} 1 × 10 ¹⁵ cm ^-2 . It simultaneously injects and activates the 2 semiconductor layer 8. For example, when boron is 1Mev, 2Mev, and 3MeV, and implanted into a substrate under a 2 × 10 ¹³ cm ⁻² injection amount condition, as shown in FIG. 19, impurity concentrations are approximately 1.7 (μm) 2.8 (μm) and 4.0 ( Maximum at depth). As a result, the impurity concentration at the bottom of the substrate can be maximized.

The semiconductor layer 8 forms an impurity diffusion region 8a. In this way, the separation region of the semiconductor device according to this embodiment is completed.

As described above, the number of implantation steps in the impurity region is reduced by using the separation structure without the channel stopper. Therefore, the number of steps for forming the resist film can be reduced, and thus the manufacturing process can be shortened. Next, a method of manufacturing a CMOS transistor using an isolation region of a semiconductor device will be described with reference to FIGS.

In FIG. 20, the first oxide film 14 of SIO ₂ is formed on the surface of the semiconductor substrate 13 to a thickness of about 30 [mu] s. On the surface of the first oxide film 14, a first semiconductor layer 15 made of polysilicon is formed to a thickness of about 500 to 2000 microseconds by the CVD method.

Thereafter, a second oxide film 16 of SIO ₂ is formed on the surface of the first semiconductor layer 15 to a thickness of about 300 GPa.

In FIG. 21, a resist film 17 having a pattern for forming a separation groove on the surface of the second oxide film 16 is formed. Thereafter, in Fig. 20, the resist film 17 is used as a mask, and grooves 18 and 19 having a depth of about 0.3 to 1.0 mu m are formed by anisotropic etching.

Next, after the resist film 17 is removed in FIGS. 23 and 24, an oxide film is formed on the inner surface of the grooves 18 and 19. At this time, the first semiconductor layer 15 is oxidized and the second oxide layer 16 is thickened.

In the side portions of the grooves 18 and 19, the second oxide film 16 and the first oxide film 14 are integrated. The oxide film thus formed is hereinafter referred to as oxide film 2.

In FIG. 25, the oxide film 20 of the bottom portion of the grooves 18 and 19 is removed by anisotropic etching to expose the semiconductor substrate 13. Then, in FIG. 26, gases such as SICL ₄ , SIHCL ₃ , SIH ₂ CL ₂ , and SIH ₄ are used by epitaxial growth on the inside of the grooves 18 and 19 and on the surface of the oxide film 20. The second semiconductor layer 21 is formed to a thickness of about 0.1 탆 at a growth rate of about 0.2 to 1.5 탆 / min and a growth temperature in the range of 700 to 1200 캜.

In order to make the surface of the semiconductor layer 21 uniform, the resist film 22 is formed flat on the surface of the semiconductor layer 21 in FIGS. 27 and 28 and etched to a predetermined depth.

In this etching, the etching rates of both are combined by mixing CCL ₄ for etching the semiconductor substrate 21 and O ₂ for etching the resist film 22. In FIG. 29, impurities in the semiconductor layer 21 are thermally diffused deep from the surface of the semiconductor substrate 1 to form the oxide film 23.

The oxide film 20 and the oxide film 23 are etched until the surface of the semiconductor layer 15 is exposed.

Thereafter, only the semiconductor layer 15 exposed in FIG. 20 is removed by etching.

Next, in FIG. 31, a resist film 20 is formed on the surface of the right half of the oxide film 20, and the resist film 25 is used as a mask, and the phosphor film is formed to a predetermined depth of the semiconductor substrate 13 on the left half. P) is injected with a constant energy value in the range of 500 KeV to 11.5 MeV and a constant injection amount in the range of 1 × 10 ^{12 to} 1 × 10 ¹⁵ cm ^-2, and thermally diffuses at a temperature of 800 to 1200 ° C for 20 minutes to 10 hours. An n-type impurity conversion region 26 is formed at the bottom of the substrate to the maximum.

At this time, the n-type impurity diffusion layer 21a is formed by simultaneously implanting and diffusing phosphorus (P) into the second semiconductor layer 21 formed in the groove 18. Next, in FIG. 32, a resist film 27 is formed on the surface of the left half of the oxide film 20 by the method described above, and boron (B) is used as the mask on the right half of the semiconductor substrate. It is implanted and diffused to a predetermined depth of (13) to form a p-type impurity diffusion region 28.

At the same time, boron (B) is injected into the second semiconductor device 21 formed in the grooves 19 at a constant value in the range of 200 KeV to 2 MeV and 1 × 10 ^{12 to} 1 × 10 ¹⁵ cm ⁻² , and then 800 to 1200 ° C. By thermal diffusion at a temperature of 20 minutes to 10 hours, a p-type impurity diffusion layer 21b is formed at the bottom of the substrate with a maximum impurity concentration.

Thereafter, by removing the resist film 27, the isolation region used for the CMOS transistor is completed as shown in FIG. Thereafter, the gate oxide film 11 is deposited and the gate electrode 7 is formed.

The gate electrode 7 is etched into a predetermined shape using a photolithography technique.

Source / drain regions 9 and 10 are then formed in each well. Next, an interlayer oxide film 24 is deposited on the front surface of the substrate. Thereafter, the contact hole 24a reaching the source / drain regions 9 and 10 is opened by the photolithography technique. The aluminum layer 29 is deposited by sputtering and etched by photolithography.

In this way, the CMOS transistor is completed as shown in FIG.

In the above embodiment, the epitaxial layer is formed to form the p-type impurity diffusion region in the second semiconductor layer formed in the groove, but instead, a metal material made of tungsten (W) may be deposited.

In this case, the CVD method is used for the mixed gases Wf ₆ and SiH ₄ or Wf ₆ and H ₂ at a temperature in the range of about ₄₀₀ to 1000 ° C. When the second semiconductor layer is formed of tungsten (W), impurities do not diffuse in this layer but diffuse only in the semiconductor substrate.

As described above, in the CMOS transistor having the isolation structure without the channel stopper, the number of impurity implantation steps can be reduced, so that the number of resist film formation steps can be reduced by half, thereby reducing the manufacturing process.

In the embodiment according to the present invention, since the channel stopper region provided in the groove bottom is not provided in the related art, the manufacturing process can be shortened.

In particular, when the semiconductor device having the structure according to this embodiment is used in a CMOS transistor, the manufacturing process can be greatly shortened, thereby increasing the reliability of the product and reducing the cost.

Claims (19)

A major surface, substantially parallel to the major surface, and comprising an impurity region of a first conductivity type having a maximum impurity concentration band at a depth of 1.7 μm, 2.8 μm, or 4.0 μm from the main surface; Between the band is composed of a semiconductor substrate (1) having a low impurity concentration of the first conductivity type, and a separation groove (6) filled with a separation material (11) extending from the main surface to the band and having a sidewall and a bottom, The band extends laterally from the bottom and sidewall portions of the groove 6 in contact with the band and wherein the substrate 1, the maximum impurity concentration band and the low impurity concentration band are of the same conductivity type. Sound semiconductor device. 2. The device of claim 1, wherein the isolation material is silicon oxide (Sio ₂ ) (11). 2. The device of claim 1, wherein the separation material is a thermal expansion coefficient equal to the thermal expansion coefficient of the semiconductor substrate (1). 2. The device of claim 1, wherein the isolation material comprises an oxide film (11). The device of claim 1, wherein the maximum impurity concentration is at least 1 × 10 ¹⁶ ions / cm 3. 4. The device of claim 3, wherein the substrate (1) is a silicon substrate and the separation material is made of polysilicon in contact with the substrate (1) in the zone. 4. The semiconductor device according to claim 3, wherein the substrate (1) is a silicon substrate and the separation material is composed of unitary silicon in contact with the substrate (1) in the zone. 7. The device of claim 6, wherein the groove (6) further comprises an oxide film (11) extending between each of the side walls and the polysilicon to cover the top surface of the polysilicon. The device of claim 6, wherein the polysilicon contains the first conductive impurity. 8. The device of claim 7, wherein the groove (6) further comprises an oxide film (11) extending between each sidewall and the single crystal silicon to cover the top surface of the single crystal silicon. 8. The device of claim 7, wherein the single crystal silicon contains the first conductive impurity. A semiconductor substrate 1 having an impurity region of the first shape having a maximum impurity concentration at a depth of 1.7 μm or 2.8 μm or 4.0 μm in the depth direction from the surface, and the maximum impurity concentration extends laterally from the bottom of the groove in the band. A groove 6 formed at a depth of about 0.3 μm to 1.0 μm from the surface of the semiconductor substrate 1 in the impurity region of the first conductivity type, and spaced apart from an inner side wall of the groove. An impurity diffusion region 8a of the first conductive type which is in contact with the impurity region of the first conductive type of the substrate 1 and has an impurity concentration substantially equal to that of the first conductive type is formed in the groove 6. And an oxide film 11 covering the upper surface of the impurity diffusion region 8a and the surface of the semiconductor substrate 1 while filling the space between the sidewall and the impurity diffusion region 8a. ) Of the semiconductor substrate 1 And said impurity region, said maximum impurity concentration region and said impurity diffusion region (8a) are of the same conductivity type. 13. The device of claim 12, wherein a maximum value of impurity concentration in the impurity region of the first conductivity type is 1 x 10 ¹⁶ ions / cm < 3 >. The first conductive semiconductor substrate 1 having a main surface, a groove 6 formed at a depth of about 0.3 µm to 1.0 µm from the main surface, and the groove 6 having a depth of about 0/3 µm to 1.0 µm. A pair of sidewall insulating films extending along the sidewalls of the semiconductor layer, a buried layer filling the grooves 6 surrounded by the pair of sidewall insulating films, and having a prescribed impurity concentration of the conductivity type; ) And a higher impurity concentration than the buried layer in contact with the inner surface of the sidewall insulating film of the buried layer region provided near the lower surface of the upper insulating film and the side surface of the buried layer. A device isolation semiconductor comprising a pair of conductive layers of the first conductive type extending into the grooves 6 at a depth shallower than the depth and only in the high impurity concentration region of the first conductive type in the grooves 6. Device. 15. The device of claim 14, wherein each of the pair of conductive layers comprises a low conductive layer having an impurity concentration defined for coupling with the conductive layer. The device of claim 15, wherein the pair of conductive layers and the bottom conductive layer have the same impurity concentration. 16. An outer conductive layer according to claim 15, comprising an outer conductive layer having a predetermined impurity concentration formed in contact with an outer side of said pair of inner insulating films from the surface of said semiconductor substrate 1 and covering said pair of inner insulating films and said bottom conductive layer. Semiconductor device for device isolation. The device of claim 17, wherein the pair of conductive layers, the bottom conductive layer, and the outer conductive layer have the same impurity concentration. And the lower surface portion of the upper insulating film is positioned lower than the position of the main surface of the semiconductor substrate (1).