KR960013509B1 - Method for marking electric charge storage pole - Google Patents
Method for marking electric charge storage pole Download PDFInfo
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- KR960013509B1 KR960013509B1 KR1019930012674A KR930012674A KR960013509B1 KR 960013509 B1 KR960013509 B1 KR 960013509B1 KR 1019930012674 A KR1019930012674 A KR 1019930012674A KR 930012674 A KR930012674 A KR 930012674A KR 960013509 B1 KR960013509 B1 KR 960013509B1
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- 238000003860 storage Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 72
- 239000011229 interlayer Substances 0.000 claims description 10
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000005192 partition Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 6
- 229910000040 hydrogen fluoride Inorganic materials 0.000 abstract description 5
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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Abstract
Description
제1a도 내지 제1e도는 본 발명에 따른 캐패시터의 전하저장전극을 형성하는 단계를 도시한 단면도.1A to 1E are cross-sectional views illustrating a step of forming a charge storage electrode of a capacitor according to the present invention.
제2a도 및 제2b도는 상기 제1c도 및 제1d도에 각기 적용되는 마스크 배치도.2A and 2B are mask arrangement diagrams applied to FIGS. 1C and 1D, respectively.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film
3 : 게이트 전극 4 : 소오스/드레인 전극3: gate electrode 4: source / drain electrode
5 : 비트라인 6 : 층간 절연막5 bit line 6 interlayer insulation film
7 : 제1산화막 8 : 콘택홀7: first oxide film 8: contact hole
9 : 제1도전층 10 : 제2산화막9: first conductive layer 10: second oxide film
11 : 제2도전층 12 : 제3산화막11: second conductive layer 12: third oxide film
13 : 제3도전층 14 : 요흠13: 3rd conductive layer 14: Yo-Hum
15 : 전하저장전극 21 : 제1마스크15: charge storage electrode 21: the first mask
22 : 제2마스크22: second mask
본 발명은 고집적 반도체 소자의 제조공정중 캐패시터의 전하저장전극을 형성하는 방법에 관한 것으로, 특히 실린더형 구조에 뚜껑과 칸막이 형상을 복합하여 전하저장전극을 3차원 구조로 형성시켜 전하저장전극의 유효 표면적을 증대시키는 캐패시터의 전하저장전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a charge storage electrode of a capacitor during a manufacturing process of a highly integrated semiconductor device. In particular, the cap and partition shapes are combined in a cylindrical structure to form a charge storage electrode in a three-dimensional structure, and thus the charge storage electrode is effectively used. A method of forming a charge storage electrode of a capacitor that increases the surface area.
일반적으로, 반도체 소자가 고집적화 되어감에 따라 단위셀당 적용할 수 있는 캐패시터의 유효 표면적이 줄어들어 셀 동작에 필요한 충분한 전하량을 확보하기 위하여, 3차원화된 여러가지 형태의 전하저장전극이 연구개발되어져 왔다. 그중에 대표적인 실린더나 핀구조등은 반도체 소자가 고집적화 되어감에 따라 유효 표면적을 증가시키기 위해 핀수를 늘이거나 실린더 높이를 높여야 하며, 결국 토플러지(topology)가 증대되어 콘택 공정 및 리소그라피 공정 등에 문제가 될 뿐 아니라 반도체 소자의 제조에 어려움이 따른다.In general, as semiconductor devices have been highly integrated, various types of three-dimensional charge storage electrodes have been researched and developed in order to reduce the effective surface area of a capacitor that can be applied per unit cell and to secure sufficient amount of charge required for cell operation. Among them, typical cylinders and fin structures need to increase the number of pins or increase the cylinder height in order to increase the effective surface area as semiconductor devices become highly integrated. In addition, there is a difficulty in manufacturing a semiconductor device.
따라서, 본 발명은 반도체 소자의 고집적화에 따라 제한된 셀 면적내에서 캐패시터의 충분하 충전 용량을 얻을 수 있도록 하기 위하여, 실린더형 구조에 뚜껑과 칸막이 형상을 복합 형성하는 방법으로 전하저장전극을 형성시키므로써, 기본적인 실린더형 구조 또는 핀형 구조보다 전하저장전극의 유효 표면적을 증가시켜 제한된 셀 면적내에서 캐패시터의 충분한 충전용량을 얻을 수 있도록 한 캐패시터의 전하저장전극 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention forms a charge storage electrode by forming a cap and a partition in a cylindrical structure in order to obtain a sufficient charge capacity of a capacitor within a limited cell area in accordance with high integration of semiconductor devices. It is an object of the present invention to provide a method for forming a charge storage electrode of a capacitor which increases the effective surface area of the charge storage electrode than a basic cylindrical structure or a fin structure to obtain a sufficient charge capacity of the capacitor within a limited cell area.
이러한 목적을 달성하기 위한 본 발명의 전하저장전극 형성방법은 실리콘 기판(1)상에 소정의 트랜지스터, 필드 산화막(2), 비트라인(5) 및 층간 절연막(6)을 형성하고, 상기 층간 절연막(6) 상부에 제1산화막(7)을 증착 형성한 다음, 마스크 공정 및 식각공정으로 상기 제1산화막(7) 및 층간 절연막(6)의 소정부분을 상기 실리콘 기판(1)이 노출될 때까지 식각하여 전하저장전극용 콘택홀(8)을 형성하는 단계와, 상기 콘택홀(8)과 제1산화막(7) 상부에 제1도전층(9)을 형성한 다음, 상기 제1도전층(9) 상부에 순차적으로 제2산화막(10), 제2도전층(11) 및 제3산화막(12)을 형성하는 단계와, 상기 제3산화막(12)상에 제1마스크(21)를 위치시키고, 이를 사용하여 상기 제3산화막(12), 제2도전층(11) 및 제2산화막(10)을 순차적으로 노출된 부분을 식각하여 패턴화하는 단계와, 상기 제3산화막(12), 제2도전층(11) 및 제2산화막(10)의 노출부분과 상기 제1도전층(9)의 노출부분에 제3도전층(13)을 전반적으로 증착 형성하는 단계와, 상기 제3도전층(13)상에 제2마스크(22)를 위치시키고, 이를 사용하여 제3도전층(13), 제3산화막(12), 제2도전층(11) 및 제1도전층(9)의 노출부분을 식각하여 중앙부분에 요흠(14)이 형성된 전하저장전극 영역을 패턴화하는 단계와, 상기 패턴화된 제1,2 및 3 도전층(9,11 및 13)사이의 제2 및 3산화막(10 및 12)을 저압기상 HF 식각장치에서 식각하여, 제1도전층(9)을 전하저장전극 패드로 하고 제3도전층(13)을 뚜껑으로 그리고 제2도전층(11)을 칸막이로 하여 구성된 캐패시터의 전하저장전극(15)을 형성하는 단계로 이루어지는 것을 특징으로 한다.In the charge storage electrode forming method of the present invention for achieving this purpose, a predetermined transistor, a field oxide film (2), a bit line (5) and an interlayer insulating film (6) are formed on a silicon substrate (1), and the interlayer insulating film is formed. (6) When the silicon substrate 1 is exposed to a predetermined portion of the first oxide film 7 and the interlayer insulating film 6 by depositing and forming a first oxide film 7 thereon, by a mask process and an etching process. Etching to form a contact hole 8 for a charge storage electrode, and forming a first conductive layer 9 on the contact hole 8 and the first oxide layer 7, and then forming the first conductive layer. (9) sequentially forming a second oxide film 10, a second conductive layer 11, and a third oxide film 12 thereon, and first mask 21 on the third oxide film 12. Positioning and patterning the exposed portions of the third oxide layer 12, the second conductive layer 11, and the second oxide layer 10 by sequentially using the same; Depositing the third conductive layer 13 on the exposed portions of the trioxide oxide film 12, the second conductive layer 11 and the second oxide film 10, and the exposed portions of the first conductive layer 9; The second mask 22 is positioned on the third conductive layer 13, and the third mask layer 13, the third oxide layer 12, the second conductive layer 11, and the first conductive layer 13 are disposed thereon. Etching the exposed portion of the conductive layer 9 to pattern the charge storage electrode region in which the recess 14 is formed in the center portion, and the patterned first, second and third conductive layers 9, 11 and 13. The second and third oxide films 10 and 12 therebetween are etched by a low pressure gaseous HF etching apparatus, so that the first conductive layer 9 is used as a charge storage electrode pad and the third conductive layer 13 is covered by a lid. It is characterized in that it comprises the step of forming the charge storage electrode 15 of the capacitor composed of the layer 11 as a partition.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1e도는 본 발명에 따른 캐패시터의 전하저장전극을 형성하는 단계를 도시한 단면도로서, 제1a도는 실리콘 기판(1)상에 게이트 전극(3), 소오스/드레인 전극(4)등으로 반도체 소자의 셀을 구성하는 트랜지스터와 필드 산화막(2), 비트라인(5) 등을 형성한 후에 층간 절연막(6)을 증착 열처리하여 평탄화 하고, 상기 평탄화 된 층간 절연막(6) 상부에 제1산화막(7)을 증착 형성한 다음, 전하저장전극을 콘택하기 위해 마스크 공정 및 식각공정으로 상기 제1산화막(7) 및 층간 절연막(6)의 소정부분을 실리콘 기판(1)이 노출될 때까지 식각하여 콘택홀(8)을 형성한 상태를 도시한 것이다.1A to 1E are cross-sectional views illustrating a step of forming a charge storage electrode of a capacitor according to the present invention, and FIG. 1A shows a gate electrode 3, a source / drain electrode 4, etc. on a silicon substrate 1; After the transistors, the field oxide film 2, the bit line 5, and the like which form the cell of the semiconductor device are formed, the interlayer insulating film 6 is deposited by heat treatment to be flattened, and the first interlayer insulating film 6 is first planarized. After the oxide film 7 is deposited, a predetermined portion of the first oxide film 7 and the interlayer insulating film 6 are exposed by a mask process and an etching process to contact the charge storage electrode until the silicon substrate 1 is exposed. The state in which the contact hole 8 is formed by etching is illustrated.
상기 제1산화막(7)은 HTO이다.The first oxide film 7 is HTO.
제1b도는 상기 콘택홀(8) 및 상기 제1산화막(7) 상부에 제1도전층(9)을 형성하고, 상기 제1도전층(9)상부에 순차적으로 제2산화막(10), 제2도전층(11) 및 제3산화막(12)을 형성한 상태를 도시한 것이다.FIG. 1B illustrates a first conductive layer 9 formed on the contact hole 8 and the first oxide layer 7, and sequentially on the first conductive layer 9, the second oxide layer 10 and the second conductive layer 9. The state in which the second conductive layer 11 and the third oxide film 12 are formed is shown.
상기 제1도전층(9) 및 제2도전층(11)은 인-시투 포스포러스 도프 폴리실리콘(in-situ phosphrus doped polysilicon)이며, 상기 제2도 전층(11)의 두께는 500~1000Å이다. 그리고 상기 제2 및 3산화막(10 및 12)은 BPSG로 두껍게 증착 형성한다.The first conductive layer 9 and the second conductive layer 11 are in-situ phosphrus doped polysilicon, and the thickness of the second conductive layer 11 is 500 to 1000 kPa. . The second and third oxide films 10 and 12 are formed by thick deposition of BPSG.
제1c도는 상기 제1b도의 구조하에서 제2a도에 도시된 제1마스크(21)를 사용하여, 제3산화막(12), 제2도전층(11) 및 제2산화막(10)을 순차적으로 노출된 부분을 식각하여 패턴화한 상태를 도시한 것이다.FIG. 1C sequentially exposes the third oxide film 12, the second conductive layer 11, and the second oxide film 10 using the first mask 21 shown in FIG. 2A under the structure of FIG. 1B. The patterned state is shown by etching the parts.
제1d도는 상기 패턴화된 제3산화막(12), 제2도전층(11) 및 제2산화막(10)의 노출부분과 상기 제1도전층(9)의 노출된 부분의 상부에 전반적으로 인-시투 포스포러스 도프 폴리실리콘을 500~1000Å의 두께로 증착하여 제3도전층(13)을 형성한 다음, 제2b도에 도시된 제2마스크(22)를 사용하여 먼저 제3도전층(13)의 노출부분을 식각하고, 이어서 제3산화막(12)의 노출부분을 식각하며, 계속해서 상기 제3산화막(12)의 식각으로 일부가 노출된 제2도전층(11)과 상기 제3도전층(13)의 식각으로 일부가 노출된 제1도전층(9)을 동시에 식각하여 중앙부분에 요흠(14)이 형성된 전하저장전극 영역이 패턴화된 상태를 도시한 것이다.FIG. 1D is generally formed on the exposed portions of the patterned third oxide layer 12, the second conductive layer 11, and the second oxide layer 10 and the exposed portions of the first conductive layer 9. A third conductive layer 13 is formed by depositing a situ phosphor-doped polysilicon to a thickness of 500 to 1000 GPa, and then using the second mask 22 shown in FIG. 2B, firstly, the third conductive layer 13 is formed. ), And then the exposed portion of the third oxide film 12 is etched, and the second conductive layer 11 and the third conductive layer partially exposed by etching the third oxide film 12 are subsequently etched. The first conductive layer 9 partially exposed by etching the layer 13 is simultaneously etched to form a patterned state of the charge storage electrode region in which the recess 14 is formed at the center portion.
여기서 주목할 점은 제2마스크(22)를 1회 사용하면서 전하저장전극 영역을 설정할 뿐만 아니라 중앙부분에 요흠(14)을 형성할 수 있다는 점이다.Note that the use of the second mask 22 once may not only set the charge storage electrode region but also form the recess 14 in the center portion.
한편, 상기 제1마스크(21)와 제2마스크(22)의 간격은 캐패시터 특성을 저하시키지 않는 범위에서 선택되는 제3도전층(13)의 두께를 고려하고 마스크이 오배열 여유도(misalign margin)를 고려하여 정한다.On the other hand, the distance between the first mask 21 and the second mask 22 takes into account the thickness of the third conductive layer 13 selected in the range that does not lower the capacitor characteristics, the mask misaligned margin (misalign margin) It is decided by considering.
제1e도는 상기 제1d도의 구조하에서 제2산화막(10) 및 제3산화막(12)을 저압기상 HF(low pressure vapor hydrogen fluoride) 식각장치에서 완전히 식각하여, 제1도전층(9)을 전하저장전극 패트(pad)로 하고 제3도전층(13)을 뚜껑으로 그리고 제2도전층(11)을 칸막이로 하여 구성된 캐패시터의 전하저장전극(15)을 형성한 상태를 도시한 것이다.In FIG. 1E, the second oxide film 10 and the third oxide film 12 are completely etched in a low pressure vapor hydrogen fluoride (HF) etching apparatus under the structure of FIG. 1D to charge and store the first conductive layer 9. The state in which the charge storage electrode 15 of the capacitor formed by using an electrode pad, a third conductive layer 13 as a lid, and a second conductive layer 11 as a partition is formed.
상기 저압기상 HF 식각장치로 BPSG인 제2 및 3 산화막(10 및 12)을 식각할 시 HTO인 제1산화막(7)은 BPSG와 HTO의 식각선택비에 의해 제2 및 3산화막(10 및 12)이 식가되는 동안 제1산화막(7)은 손상되지 않는데, 이는 저압기상 HF 식각장치에서 BPSG와 HTO의 선택식각비가 H2O의 분압을 조절함에 따라 1000 : 1 이상까지 조절가능한 특성이 있기 때문이다.When the second and third oxide films 10 and 12, which are BPSG, are etched by the low pressure gaseous HF etching apparatus, the first oxide film 7, which is HTO, is formed by the second and third oxide films 10 and 12 by the etching selectivity of BPSG and HTO. The first oxide film 7 is not damaged during the cooling process, since the selective etching ratio of BPSG and HTO in the low pressure gaseous HF etching apparatus is adjustable to 1000: 1 or more as the partial pressure of H 2 O is adjusted. to be.
한편, BPSG와 인-시투 포스포러스 도프 폴리실리콘층의 적층수가 많은 경우 BPSG/HTO 식각 선택비를 높이기 위하여 기상 HF 식각장치의 H2O 압력을 낮추어 주면 된다.On the other hand, when the number of BPSG and the in-situ phosphorus-doped polysilicon layer is large, the H 2 O pressure of the gas phase HF etching apparatus may be lowered in order to increase the BPSG / HTO etching selectivity.
상술한 바와같이 본 발명은 제1도전층으로 전하저장전극의 패드를 구성한 다음, 그 상부에 BPSG 산화막과 전하저장전극용 폴리실리콘층을 차례로 적층하되, 최종적으로 폴리실리콘층으로 전체를 덮어 뚜껑을 형성하여, 실린더형 구조에 뚜껑과 칸막이 형상이 복합되어 구성된 캐패시터의 전하저장전극이 형성되도록 하므로써, 전하저장전극의 유효 표면적을 증가시켜 제한된 셀 면적내에서 캐패시터의 충분한 충전용량을 얻을 수 있을 뿐만 아니라 제조공정상 어려움이 없어 생산성 향상에도 기여할 수 있다.As described above, the present invention configures the pad of the charge storage electrode as the first conductive layer, and then sequentially stacks the BPSG oxide layer and the polysilicon layer for the charge storage electrode on top thereof, finally covering the whole with the polysilicon layer to cover the lid. By forming the cap and partition structure in a cylindrical structure, the charge storage electrode of the capacitor formed is formed, thereby increasing the effective surface area of the charge storage electrode to obtain a sufficient charge capacity of the capacitor within the limited cell area. There is no difficulty in the manufacturing process, which can contribute to productivity improvement.
Claims (2)
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| KR1019930012674A KR960013509B1 (en) | 1993-07-07 | 1993-07-07 | Method for marking electric charge storage pole |
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| KR1019930012674A KR960013509B1 (en) | 1993-07-07 | 1993-07-07 | Method for marking electric charge storage pole |
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| KR960013509B1 true KR960013509B1 (en) | 1996-10-05 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101994073B1 (en) | 2019-03-13 | 2019-06-27 | 조현호 | Jigs for surface treatment of steering linkage equipment for vehicles |
| KR102532388B1 (en) | 2022-12-29 | 2023-05-15 | 주식회사 엠브이 | Painting method for injection products for vehicles |
| KR102610624B1 (en) | 2022-12-29 | 2023-12-06 | 주식회사 엠브이 | Defect detection method for painted products of vehicles |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100393961B1 (en) * | 1996-11-06 | 2003-11-20 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor of semiconductor device |
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1993
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101994073B1 (en) | 2019-03-13 | 2019-06-27 | 조현호 | Jigs for surface treatment of steering linkage equipment for vehicles |
| KR102532388B1 (en) | 2022-12-29 | 2023-05-15 | 주식회사 엠브이 | Painting method for injection products for vehicles |
| KR102610624B1 (en) | 2022-12-29 | 2023-12-06 | 주식회사 엠브이 | Defect detection method for painted products of vehicles |
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| KR950004524A (en) | 1995-02-18 |
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