KR960011711A - Page selection circuit between register pages using register page pointer - Google Patents

Page selection circuit between register pages using register page pointer Download PDF

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Publication number
KR960011711A
KR960011711A KR1019940024753A KR19940024753A KR960011711A KR 960011711 A KR960011711 A KR 960011711A KR 1019940024753 A KR1019940024753 A KR 1019940024753A KR 19940024753 A KR19940024753 A KR 19940024753A KR 960011711 A KR960011711 A KR 960011711A
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KR
South Korea
Prior art keywords
page
register
selection circuit
selecting
bit
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Application number
KR1019940024753A
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Korean (ko)
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KR960016401B1 (en
Inventor
김상범
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019940024753A priority Critical patent/KR960016401B1/en
Publication of KR960011711A publication Critical patent/KR960011711A/en
Application granted granted Critical
Publication of KR960016401B1 publication Critical patent/KR960016401B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

본 발명은 마이크로 콘트롤러 내부에 개개의 분리된 페이지를 가지고 있는 레지스터 파일에 있어 출발페이지와 도착페이지 모두를 동시에 선택할 수 있는 레지스터 페이지 포인터 바이트를 가지고 있는 레지스터 페이지 선택회로에 관한 것이다.The present invention relates to a register page selection circuit having a register page pointer byte for selecting both a start page and a destination page at the same time in a register file having individual separate pages inside a microcontroller.

이를 위하여 각각의 분리된 다수의 페이지들로 구성되며 각 페이지내에는 다수의 레지스터들이 있는 레지스터 파일, 출발페이지 비트와 도착페이지 모두를 선택하는 레지스터 페이지 포인터 바이트, 출발페이지 비트와 도착페이지 비트중 하나를 선택하는 멀티플렉서 수단 및 멀티플렉서 수단의 출력을 디코더하는 디코더 수단으로 구성된 레지스터 페이지 선택회로이다.It consists of a number of separate pages, each of which contains a register file with multiple registers, a register page pointer byte that selects both the start page bit and the destination page, one of the start page bit and the destination page bit. A register page selection circuit is composed of multiplexer means for selecting and decoder means for decoding the output of the multiplexer means.

Description

레지스터 페이지 포인터를 이용한 레지스터 페이지간의 페이지 선택회로Page selection circuit between register pages using register page pointer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따라 레지스터 페이지 포인터를 이용한 레지스터 페이지간의 페이지 선택을 보여주는 실시예의 구성도,2 is a block diagram of an embodiment showing page selection between register pages using a register page pointer according to the present invention;

제3도는 본 발명에 따라 레지스터 파일의 페이지를 확장시킨 실시예의 구성도이다.3 is a block diagram of an embodiment in which pages of a register file are expanded according to the present invention.

Claims (5)

레지스터 파일의 레지스터 페이지 선택회로에 있어서, 각각의 분리된 페이지내에 다수의 레지스터들이 있는 레지스터 파일; 상기의 레지스터 파일의 출발페이지와 도착페이지를 동시에 선택하는 레지스터 페이지 포인터 바이트; 출발페이지 비트와 도착페이지 비트중 하나를 선택하는 멀티플렉서 수단; 및 상기의 멀티플렉서 수단의 출력을 디코더하여 상기의 분리된 페이지중 어느 한 페이지를 선택하기 위한 선택신호를 발생하는 디코더 수단으로 구성된 것을 특징으로 하는 레지스터 페이지 선택회로.1. A register page selection circuit of a register file, comprising: a register file having a plurality of registers in each separate page; A register page pointer byte for simultaneously selecting a start page and a destination page of the register file; Multiplexer means for selecting one of a departure page bit and an arrival page bit; And decoder means for decoding the output of said multiplexer means to generate a selection signal for selecting any one of said separated pages. 제1항에 있어서, 상기의 멀티플렉서 수단에 출발페이지 비티와 도착 페이지 비트를 선택하기 위하여 상기의 멀티플렉서 수단에 공급되는 출발 또는 페이지 선택신호로 구성된 것을 특징으로 하는 레지스터 페이지 선택회로.2. The register page selection circuit according to claim 1, characterized by comprising a start or page select signal supplied to said multiplexer means for selecting a start page bit and an arrival page bit to said multiplexer means. 제1항에 있어서, 서로 다른 분리된 4개의 페이지로 구분된 레지스터 파일에 출발 또는 도착페이지를 선택하기 위한 4비트의 레지스터 페이지 포인터 바이트로 구성된 것을 특징으로 하는 레지스터 페이지 선택회로.2. The register page selection circuit according to claim 1, wherein a register page pointer byte of four bits for selecting a start or destination page is included in a register file divided into four separate pages. 제1항에 있어서, 서로 다른 분리된 16개의 페이지로 구분된 레지스터 파일에 출발 또는 도착페이지를 선택하기 위한 8비트의 레지스터 페이지 포인터 바이트로 구성된 것을 특징으로 하는 레지스터 페이지 선택회로.2. The register page selection circuit according to claim 1, characterized in that it consists of 8-bit register page pointer bytes for selecting a start or destination page in a register file divided into 16 separate pages. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940024753A 1994-09-29 1994-09-29 Page selecting circuit of register pages using register page pointer KR960016401B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940024753A KR960016401B1 (en) 1994-09-29 1994-09-29 Page selecting circuit of register pages using register page pointer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940024753A KR960016401B1 (en) 1994-09-29 1994-09-29 Page selecting circuit of register pages using register page pointer

Publications (2)

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KR960011711A true KR960011711A (en) 1996-04-20
KR960016401B1 KR960016401B1 (en) 1996-12-11

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100402293B1 (en) * 2000-07-20 2003-10-22 대한민국 Dying Methods of Purple Sweetpotato Pigment
KR20200145897A (en) * 2019-06-19 2020-12-31 대한민국(농촌진흥청장) Method for producing extracts of sweet potato with enhanced antioxidative activity and extracts of sweet potato produced by the same method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100402293B1 (en) * 2000-07-20 2003-10-22 대한민국 Dying Methods of Purple Sweetpotato Pigment
KR20200145897A (en) * 2019-06-19 2020-12-31 대한민국(농촌진흥청장) Method for producing extracts of sweet potato with enhanced antioxidative activity and extracts of sweet potato produced by the same method

Also Published As

Publication number Publication date
KR960016401B1 (en) 1996-12-11

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