KR960008980A - Method of forming protective film for semiconductor device - Google Patents

Method of forming protective film for semiconductor device Download PDF

Info

Publication number
KR960008980A
KR960008980A KR1019940019066A KR19940019066A KR960008980A KR 960008980 A KR960008980 A KR 960008980A KR 1019940019066 A KR1019940019066 A KR 1019940019066A KR 19940019066 A KR19940019066 A KR 19940019066A KR 960008980 A KR960008980 A KR 960008980A
Authority
KR
South Korea
Prior art keywords
protective film
forming
fuse
semiconductor device
repair
Prior art date
Application number
KR1019940019066A
Other languages
Korean (ko)
Other versions
KR0143033B1 (en
Inventor
용창범
김상철
조광행
이신국
백동원
김세정
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940019066A priority Critical patent/KR0143033B1/en
Publication of KR960008980A publication Critical patent/KR960008980A/en
Application granted granted Critical
Publication of KR0143033B1 publication Critical patent/KR0143033B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의 보호막 형성방법에 관한 것으로, 리패어를 위한 웨이퍼 정렬 불량 또는 레이져 빔의 크기 변화로 인한 휴즈지지 폴리 라인의 손상을 방지하기 위해 리패어 휴즈 박스의 폴리 휴즈의 소정부분만 노출시키므로써 리패어 다이의 수율저하를 방지할 수 있도록 한 반도체 소자의 보호막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a protective film of a semiconductor device, wherein only a predetermined portion of a poly fuse of a repair fuse box is exposed to prevent damage to a fuse supporting poly line due to a misalignment of a wafer for repair or a change in the size of a laser beam. The present invention relates to a method of forming a protective film for a semiconductor device, by which a yield reduction of a repair die can be prevented.

Description

반도체 소자의 보호막 형성방법Method of forming protective film for semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따라 휴즈 박스 부위에 형성된 보호막을 설명하기 위한 평면도.2 is a plan view for explaining a protective film formed on the fuse box in accordance with the present invention.

Claims (2)

소자 형성공정이 진행된 소정의 기판상의 소정부위에 폴리 실리콘을 증착하고 패터닝하여 폴리 휴즈(2) 및 휴즈지지 폴리라인(3)으로 구성된 휴즈 박스(1)를 형성시킨 상태에서, 리패어 공정시 레이져 빔의 크기 변화에 의한 상기 휴즈지지 폴리라인(3)의 손상을 방지하기 위한 반도체 소자의 보호막 형성방법에 있어서, 상기 휴즈 박스(1)가 형성된 소정의 기판(1)상부에 보호막(4A)을 형성시킨 후 마스크를 사용하여 사진 및 식각공정에 의해 상기 폴리 휴즈(2)의 소정부분만 노출되도록 상기 보호막(4A)을 제거시키는 것을 특징으로 하는 반도체 소자의 보호막 형성방법.In the state of forming a fuse box 1 formed of a poly fuse 2 and a fuse supporting polyline 3 by depositing and patterning polysilicon on a predetermined portion on a predetermined substrate on which the device forming process is performed, the laser during the repair process In a method of forming a protective film of a semiconductor device for preventing damage to the fuse supporting polyline 3 due to a change in the size of a beam, a protective film 4A is formed on a predetermined substrate 1 on which the fuse box 1 is formed. And forming the protective film (4A) so that only a predetermined portion of the poly fuse (2) is exposed by a photo and etching process using a mask after forming. 제1항에 있어서, 상기 보호막(4A)은 산화막 및 질화막인 것을 특징으로 하는 반도체 소자의 보호막 형성방법.A method according to claim 1, wherein the protective film (4A) is an oxide film and a nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940019066A 1994-08-02 1994-08-02 Protection film formation method in semiconductor device KR0143033B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940019066A KR0143033B1 (en) 1994-08-02 1994-08-02 Protection film formation method in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940019066A KR0143033B1 (en) 1994-08-02 1994-08-02 Protection film formation method in semiconductor device

Publications (2)

Publication Number Publication Date
KR960008980A true KR960008980A (en) 1996-03-22
KR0143033B1 KR0143033B1 (en) 1998-08-17

Family

ID=19389686

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940019066A KR0143033B1 (en) 1994-08-02 1994-08-02 Protection film formation method in semiconductor device

Country Status (1)

Country Link
KR (1) KR0143033B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990003718A (en) * 1997-06-26 1999-01-15 김영환 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990003718A (en) * 1997-06-26 1999-01-15 김영환 Semiconductor device

Also Published As

Publication number Publication date
KR0143033B1 (en) 1998-08-17

Similar Documents

Publication Publication Date Title
KR960030451A (en) Diffusion mask and method for manufacturing pn junction device using the same
KR960008980A (en) Method of forming protective film for semiconductor device
KR960026867A (en) Manufacturing method of semiconductor device
KR970018106A (en) Multilayer insulating film removal method to facilitate the repair of semiconductor devices
KR960008978A (en) Alignment mark protection method of semiconductor device
KR970067707A (en) Method of manufacturing semiconductor device
KR960002703A (en) Semiconductor manufacturing method
KR970023829A (en) Pattern formation method of semiconductor device
KR970052879A (en) Manufacturing method of semiconductor device
KR960039113A (en) How to form an alignment mark
KR970053427A (en) Method of forming mask alignment key in semiconductor device having trench isolation region
KR940010216A (en) Manufacturing Method of Semiconductor Device
KR950025874A (en) Method for manufacturing gate electrode of semiconductor device
KR970030390A (en) A wafer structure for a semiconductor device
KR980003863A (en) Method for forming fine pattern of semiconductor device
KR960026539A (en) Semiconductor device manufacturing method
KR940016673A (en) Method for manufacturing memory cell array of highly integrated semiconductor memory device
KR960042913A (en) Alignment mark protection method in the semiconductor device planarization process
KR950027967A (en) How to make photomask
KR940018930A (en) Planarization method of semiconductor device
KR980005296A (en) Reticle for contact photo of semiconductor device and contact formation method using same
KR960026398A (en) Method for manufacturing metal wiring of semiconductor device
KR940022787A (en) Semiconductor Device Insulation Method
KR970077196A (en) METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR
KR970072411A (en) Semiconductor device manufacturing method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110325

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee