KR960008850A - Logic level shift circuit - Google Patents

Logic level shift circuit Download PDF

Info

Publication number
KR960008850A
KR960008850A KR1019940020911A KR19940020911A KR960008850A KR 960008850 A KR960008850 A KR 960008850A KR 1019940020911 A KR1019940020911 A KR 1019940020911A KR 19940020911 A KR19940020911 A KR 19940020911A KR 960008850 A KR960008850 A KR 960008850A
Authority
KR
South Korea
Prior art keywords
logic level
high voltage
circuit
shift circuit
level shift
Prior art date
Application number
KR1019940020911A
Other languages
Korean (ko)
Other versions
KR0138624B1 (en
Inventor
김주영
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940020911A priority Critical patent/KR0138624B1/en
Publication of KR960008850A publication Critical patent/KR960008850A/en
Application granted granted Critical
Publication of KR0138624B1 publication Critical patent/KR0138624B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Abstract

본 발명은 로직 레벨 쉬프트 회로에 관한 것으로, Vcc 파워를 갖는 CMOS게이트 회로의 로직 레벨을 고전압용 게이트 회로의 로직 레벨로 쉬프트 시키고 쉬프트시키는 과정에서 발생되는 핫 캐리어 이펙트(Hot Carrier Effect)발생을 억제하기 위한 하프 래치방식의 로직 레벨 쉬프트 회로에 관해 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic level shift circuit, and to suppress the occurrence of a hot carrier effect caused by shifting and shifting the logic level of a CMOS gate circuit having Vcc power to the logic level of a high voltage gate circuit. A half latch logic level shift circuit is described.

Description

로직 레벨 쉬프트 회로Logic level shift circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 로직 레벨 쉬프트 회로도.1 is a logic level shift circuit diagram in accordance with the present invention.

Claims (3)

Vcc 파워를 갖는 CM0S 게이트 회로의 출력신호를 입력으로 하고, 게이트 단자로 Vcc 파워가 공급되는 고전압용 nM0S 패스트랜지스터와, 상기 고전압용 nM0S 패스 트랜지스터의 출력신호를 입력으로 하고, Vpp단자 및 접지간에 접속된 고전압용 인버터회로와, 상기 고전압용 인버터 회로의 출력신호를 입력으로 하고, 상기 Vpp 단자 및 고전압용 인버터 회로간에 접속된 하프 래치회로로 구성되는 것을 특징으로 하는 로직 레벨쉬프트 회로.The output signal of the CM0S gate circuit having the Vcc power is input, and the high voltage nM0S fast transistor to which the Vcc power is supplied to the gate terminal and the output signal of the high voltage nM0S pass transistor are input, and are connected between the Vpp terminal and the ground. And a half latch circuit connected between the high voltage inverter circuit and the output signal of the high voltage inverter circuit and connected between the Vpp terminal and the high voltage inverter circuit. 제1항에 있어서, 상기 고전압용 인버터 회로는 전원단자 및 노드(D)간에 직렬접속되는 pMOS 트랜지스터와, 상기 노드(D) 및 접지간에 직렬접속되는 pMOS 트랜지스터로 접속 구성되는 것을 특징으로 하는 로직 레벨 쉬프트 회로.The logic level of claim 1, wherein the high voltage inverter circuit comprises a pMOS transistor connected in series between a power supply terminal and a node D, and a pMOS transistor connected in series between the node D and ground. Shift circuit. 제1항에 있어서, 상기 하프 래치회로는 전원단자 및 노드(B)간에 pMOS 트랜지스터가 직렬로 접속 구성되는 것을 특징으로 하는 로직 레벨 쉬프트 회로.2. The logic level shift circuit as set forth in claim 1, wherein said half latch circuit comprises a pMOS transistor connected in series between a power supply terminal and a node (B). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940020911A 1994-08-24 1994-08-24 Circuit for logic level shift KR0138624B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940020911A KR0138624B1 (en) 1994-08-24 1994-08-24 Circuit for logic level shift

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940020911A KR0138624B1 (en) 1994-08-24 1994-08-24 Circuit for logic level shift

Publications (2)

Publication Number Publication Date
KR960008850A true KR960008850A (en) 1996-03-22
KR0138624B1 KR0138624B1 (en) 1998-06-15

Family

ID=19391025

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940020911A KR0138624B1 (en) 1994-08-24 1994-08-24 Circuit for logic level shift

Country Status (1)

Country Link
KR (1) KR0138624B1 (en)

Also Published As

Publication number Publication date
KR0138624B1 (en) 1998-06-15

Similar Documents

Publication Publication Date Title
KR970051145A (en) Potential generator
KR900013380A (en) Voltage control circuit
KR930003556A (en) Progressive Turn-On CMOS Driver
KR880001108A (en) CMOS input circuit
KR910002127A (en) Power switching circuit
KR900002558A (en) Output circuit
KR920001523A (en) Semiconductor integrated circuit including detection circuit
KR950026101A (en) Ring oscillation circuit
KR960008850A (en) Logic level shift circuit
KR960027331A (en) Buffer circuit and bias circuit
KR950015377A (en) Address transition detection circuit
KR970055396A (en) Delay circuit
KR970049214A (en) High voltage detection circuit
KR970024600A (en) Level shift circuit
KR970701450A (en) Low-voltage BiCMOS digital delay chain suitable for operation over a wide power supply range
KR950015749A (en) Power Delay Circuit of Semiconductor Memory Device
KR940003164A (en) Operational Amplifier
KR970012732A (en) Delay circuit of semiconductor device
KR970003935A (en) Logic and level conversion circuit and semiconductor device
KR970013754A (en) Level shift circuit
KR910007239A (en) Push Pull Output Circuit
KR930005370A (en) Input circuit
KR950020695A (en) High potential transfer circuit
KR930003546A (en) BiMOS Inverter Circuit
KR970078011A (en) Composite gate circuit and its design method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110126

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee