KR960008562Y1 - Data access relay apparatus - Google Patents

Abstract

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Description

Shared Data Access Mediation Device

1 is a block diagram of a shared data access arbitration apparatus according to the prior art.

2 is an operation signal timing diagram of a unique data access arbitration apparatus according to the prior art.

3 is a block diagram of a shared data access arbitration apparatus according to the present invention.

4 is an operation signal timing diagram of a shared data access arbitration apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

F1 ~ F4: D Flip-Flop OC1, OC2: Operation Control Unit

A1-A3, A5: AND gate A4, A6: NAND gate

B1: OR gate B2, B3: inverter

M1, M2, Ma, Mb: access request signals M3, L1, L2: access signals

N1, N2: Combined signal C1, C2: Operation switching signal

CP: Clock pulse

The present invention relates to a data access arbitration apparatus. In particular, when accessing data commonly used by multiple processors in a system such as an electronic exchange, when the data access is permitted and the data access is terminated, It immediately relates to a shared data access arbitrator that allows data access to the next processor so that multiple processors can effectively share data in a short time.

The data access arbitration apparatus according to the prior art is composed of D flip-flops (F1, F2), AND gates (A1, A2), inverter (B2), and OR gate (B1) as shown in FIG. D flip-flop (F1) is input terminal (D), (CLK), (CLR) and output terminal (Q), And a combined signal (N1) for logical sum with the access request signal (M1) according to the presence or absence of the access request signal (M1) input through the D terminal in the rising and falling sections of the clock pulse (CP) input to the CLK terminal. Output to AND gate (A1) through Q terminal The terminal outputs an operation stop signal to the CLR terminal of the D flip-flop (F2). D flip-flop (F2) is input terminal (D), (CLK), (CLK) and output terminal (Q), And outputs the combined signal N2 for the logical sum with the access request signal M2 to the AND gate A2 according to the presence or absence of the access request signal M2 inputted through the inverter B2 and the CLK terminal. and The terminal outputs the operation stop signal to the CLR terminal of the D flip-flop (F1). The inverter B2 inverts the level of the clock pulse CP and transfers it to the CLK terminal of the D flip-flop F2. The AND gates A1 and A2 receive the Q terminal outputs of the D flip-flops F1 and F2 and the access request signals M1 and M2, respectively, and logically multiply the result of the logic operation to the two input terminals of the OR gate B1. do. The OR gate B1 receives the two outputs of the AND gates A1 and A2 and performs a logical sum, and outputs an access request signal M3 when the operation result logic is '1'.

Referring to the timing diagram shown in FIG. 2, the access arbitration operation of the conventional data access arbitration apparatus configured as described above is as follows.

The access request signal M1 from the predetermined processor A is input to the D input terminal and the AND gate A1 of the D flip-flop F1 before the access request signal M2 from the predetermined processor B. At this time, the clock pulse CP is input to the CLK input terminal of the D flip-flop F1 and the clock pulse CP inverted by the inverter B2 is continuously input to the CLK input terminal of the D flip-flop F2. . D flip-flop (F1) is the rising edge of the clock pulse (CP) Detects the access request signal M1 of the processor A, outputs the combined signal N1 to the AND gate A1 through the Q terminal, and stops the combined signal N2 from being output from the D flip-flop F2. signal Outputs to CLR terminal of D flip-flop (F2) through the terminal. Thereafter, the AND gate A1 receives the combined signal N1 while the access request signal M1 is input, requests the OR gate A1 to output the access signal, and accordingly, the OR gate A1 transmits the access signal to the memory controller. The processor A accesses data according to the memory control of the memory controller. When the processor A terminates the data access and the access request signal M1 is interrupted, the AND gate A1 does not require the output of the access signal to the OR gate A1, and thus the access signal M3 is no longer output. On the other hand, the D flip-flop F1 detects the interruption of the access request signal M1 in the rising period ⓒ of the clock pulse CP generated after the interruption of the access request signal M1, and then detects the interruption of the access request signal M1 to the CLR of the D flip-flop F2. The output of the operation stop signal outputted and the combined signal N1 outputted to the AND gate are stopped. At this time, since the processor B continuously outputs the access request signal M2 to the D terminal of the AND gate A2 and the D flip-flop F2 for data access, the D flip-flop F2 is stopped at the CLR terminal. Immediately after the signal is stopped, the combined signal (N2) is output to the AND gate (A2) at the rising edge (ⓓ) of the next clock pulse. Outputs to CLR terminal of D flip-flop F1 through the terminal. Thereafter, the access request signal M3 is output to the memory controller by the logical operation of the AND gate A2 and the OR gate A1, and the memory controller causes the processor B to perform data access accordingly. In this way, the data access of the processor A and B is performed in sequence. Even if the processor A and B output the access request signal at the same time, clock pulses having opposite phases are applied to the D flip-flops F1 and F2. Since the clock pulse CP applied to the flip-flop F1 starts the rising section first, the processor A accesses data first so that a problem does not occur. However, in FIG. 2, the access request signal M1 stops immediately after the clock pulse CP rises (ⓑ), and (ⓒ) the combined signal N1 stops immediately, thereby combining in the rising section (ⓓ) of CLK. When the signal N2 is output and the access request signal M1 is interrupted immediately before the rising section ⓒ of the CLK (ⓒ), the combining signal N1 is immediately stopped, and then the combining signal in the rising section ⓓ of the CLK. Since N2 is output, the processor B can start data access only after a time delay T of at least half of the clock pulse and less than a half of the maximum clock pulse after the end of the data access of the processor A.

The conventional data access arbitration apparatus operating as described above allows data access to be sequentially shared according to the access request signals M1 and M2 of each processor, but allows data to be shared with each processor. Then, since the time delay T with the start time of the data access of the processor can be extended up to one week base of the clock pulse CP, there is a problem that the arbitration efficiency of the data access is lowered.

The present invention has been made in view of such a problem, and when a processor that terminates access to a shared data stops an access request, it immediately accepts another processor's access request and permits the processor to access data, thereby terminating the data access of one processor. It is an object of the present invention to provide a shared data access arbitration device which reduces the delay time between the start of data access and the next processor.

In order to achieve the above object, the present invention provides a 1D flip-flop for outputting a first access signal to a memory controller in response to a clock pulse and a first access request signal from a first processor; A 2D flip-flop for outputting a second access signal to the memory controller in response to the inverted clock pulse and a second access request signal from a second processor; Operation of the first D flip-flop according to an inverted first access signal from the 1D flip-flop, a first access request signal from the first processor, and a second access signal from the second D flip-flop A first operation control unit for switching a; Operate the second D flip-flop according to the inverted second access signal from the second D flip-flop, the second access request signal from the second processor, and the first access signal from the first D flip-flop. It provides a shared data access arbitration apparatus comprising a second operation control unit for switching.

Hereinafter, one preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a shared data access arbitration apparatus according to the present invention, and FIG. 4 is an operation signal timing diagram of the shared data access arbitration apparatus according to the present invention.

As shown in FIG. 3, the shared data access arbitration apparatus of the present invention includes D flip-flops F3 and F4, operation control units OC1 and OC2, and an inverter B3. D flip-flop (F3) is input terminal (D), (CLK), (PR) and output terminal (Q), Access is provided via the D terminal in the rising section of the clock pulse (CP) input through the CLK terminal in the state that the operation switching signal (C1) for controlling the output of the access signal (L1) is not input to the PR terminal Detects the request signal Ma and outputs the access signal L1 for data access to the memory controller which controls the memory in which the shared data is stored, and simultaneously outputs the inverted signal of the access signal L1. Output to the operation control unit OC1 through the terminal. D flip-flop (F4) is input terminal (D), (CLK), (PR) and output terminal (Q), A clock pulse CP inverted by the inverter B3 through the CLK terminal while the operation switching signal C2 for controlling the output of the access signal L2 is not input to the PR terminal. The access request signal Mb is sensed in the rising section of the clock pulse, and the access signal L2 for data access is output through the Q terminal, and the inverted signal of the access signal L2 is transmitted to the operation controller OC1. Output The inverter B3 inverts the signal level of the clock pulse CP and supplies it to the CLK terminal of the D flip-flop F4. The operation control unit OC1 includes an AND gate A3 and a NAND gate A4 to form the D flip-flop F3. Output operation of the D flip-flop F3 by receiving the terminal output and the access request signal Ma through the NAND gate A4 and the access signal L2 of the D flip-flop F4 through the AND gate A3. On and off. The operation control unit OC2 includes an AND gate A5 and a NAND gate A6 to form the D flip-flop F4. Output operation of the D flip-flop F4 by receiving the terminal output and the access request signal Mb through the NAND gate A6 and the access signal L1 of the D flip-flop F3 through the AND gate A5. On and off.

The operation of the shared data access arbitration apparatus of the present invention configured as described above will be described with reference to the operation signal timing diagram of FIG.

In the state where the clock pulse CP is input to the CLK terminal of the D flip-flop F3 and the clock pulse CP inverted by the inverter B3 is input to the CLK terminal of the D flip-flop F4, the processor A Outputs the access request signal Ma to the D terminal of the D flip-flop F3 and the input terminal of the NAND gate A4. Processor B then outputs the access request signal Mb to the D terminal of D flip-flop F4 and the input terminal of NAND gate A6. Thereafter, the D flip-flop F3 senses the access request signal Ma in the rising section ① of the clock pulse CP and outputs the access signal L1 for data access of the processor A to the memory controller through the Q terminal. While at the same time level Outputs to NAND gate A4 through terminal. Thereafter, the memory control unit supplied with the access signal L1 controls the memory in which the processor A establishes the shared data to access the data. At this time, the AND gate A5 is connected to the D flip-flop F4. Since there is no output, the NAND gate A6 receives the low level voltage output and the low level voltage by the access request signal L1 to output the operation switching signal C2 to the PR terminal of the D flip-flop F4. Therefore, since the D flip-flop F4 cannot output the access signal L2 through the Q terminal while the access signal L1 is outputted, data access of the processor B is impossible.

Then, when the data access of the processor A is terminated and the access request signal Ma by the processor A is terminated, the D flip-flop F3 is completed. The NAND gate A4 outputs the low level voltage to the AND gate A3 by the high level voltage output of the terminal and the high level voltage caused by the termination of the access request signal Ma. Accordingly, the AND gate A3 is a D flip-flop. The operation switching signal C1 is output to the PR terminal of (F3). By this operation switching signal C1, the D flip-flop F3 immediately stops outputting the access signal L1 through the Q terminal, and accordingly, the AND gate A5 is outputting through the D flip-flop F4 PR terminal. The output of the operation switching signal C2 is stopped. Thereafter, the D flip-flop F4 senses the access request signal Mb of the processor B in the rising period ④ of the inverted clock pulse CP, and applies the Q terminal to the access signal L2 for data access of the processor B. Output at the same time Outputs an access signal inverted level through the terminal. The processor A starts to access the shared data according to the memory control operation of the memory control unit by the access signal L2, and the operation of the D flip-flop F3 is stopped by the access signal L2 which is a roll level voltage. Data access is not possible. In this way, processors A and B access the shared data in turn. Even if processors A and B simultaneously output the access request signals Ma and Mb as D flip flops F3 and F4, D flip flops F3 and F4. Since the clock pulses having different phases are input to the clock pulse input terminal CLK of the controller, the order of shared data access between the processors A and B is unchanged, and the time delay T between the end and the start of the shared data access is the access request signal Ma. Will be less than one cycle of the clock pulse CP even if it is terminated immediately after the clock pulse CP rising period ②.

As described above, the present invention improves the arbitration efficiency of the shared data access because one processor terminates the data access and thus stops the access request signal, thereby allowing the next processor to access the data immediately.

Claims (3)

11. A shared data access arbitration apparatus, comprising: a first D flip-flop (F3) for outputting a first access signal to a memory controller in response to a clock pulse and a first access request signal from a first processor; A second D flip-flop (F4) outputting a second access signal to a memory controller in response to the inverted clock pulse and a second access request signal from a second processor; The first D according to an inverted first access signal from the first D flip-flop F3, a first access request signal from the first processor, and a second access signal from the second D flip-flop F4. A first operation controller OC1 for switching the operation of the flip-flop F3; The second access signal from the second D flip-flop F4, the second access request signal from the second processor, and the first access signal from the first D flip-flop F3; And a second operation controller (OC2) for switching the operation of the 2D flip-flop (F4). 2. The method of claim 1, wherein the first operation controller OC1 is configured to logically convert the inverted first access signal from the first D flip-flop F3 and the first access request signal from the first processor. The first flip-flop (operation switching signal) is obtained by performing a logic conversion between a first logic circuit A4, an output signal of the first logic circuit A4, and a second access signal from the second D flip-flop F4. And a second logic circuit (A3) for supplying to the F3) side. The second operation controller OC2 of claim 1, wherein the second operation controller OC2 is configured to logically convert an inverted second access signal from the second D flip-flop F4 and a second access request signal from the second processor. The second flip-flop (operation switching signal) is obtained by performing a logic conversion between a first logic circuit A6, an output signal of the first logic circuit A6, and a first access signal from the first D flip-flop F3. And a second logic circuit (A5) for supplying to the F4 side.