KR960008527A - 병렬 프로세서 장치 - Google Patents

병렬 프로세서 장치 Download PDF

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Publication number
KR960008527A
KR960008527A KR1019950028878A KR19950028878A KR960008527A KR 960008527 A KR960008527 A KR 960008527A KR 1019950028878 A KR1019950028878 A KR 1019950028878A KR 19950028878 A KR19950028878 A KR 19950028878A KR 960008527 A KR960008527 A KR 960008527A
Authority
KR
South Korea
Prior art keywords
processor unit
parallel processor
parallel
unit
processor
Prior art date
Application number
KR1019950028878A
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR960008527A publication Critical patent/KR960008527A/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Image Processing (AREA)
  • Advance Control (AREA)
  • Television Systems (AREA)
KR1019950028878A 1994-08-31 1995-08-31 병렬 프로세서 장치 KR960008527A (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6207805A JPH0877002A (ja) 1994-08-31 1994-08-31 並列プロセッサ装置

Publications (1)

Publication Number Publication Date
KR960008527A true KR960008527A (ko) 1996-03-22

Family

ID=16545795

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950028878A KR960008527A (ko) 1994-08-31 1995-08-31 병렬 프로세서 장치

Country Status (5)

Country Link
US (2) US5666169A (ko)
EP (3) EP0973101B1 (ko)
JP (1) JPH0877002A (ko)
KR (1) KR960008527A (ko)
DE (2) DE69519145T2 (ko)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0877002A (ja) * 1994-08-31 1996-03-22 Sony Corp 並列プロセッサ装置
JP3573406B2 (ja) * 1999-02-26 2004-10-06 キヤノン株式会社 画像処理装置
CN1223398C (zh) * 1999-12-23 2005-10-19 陶氏环球技术公司 催化装置
US6725360B1 (en) * 2000-03-31 2004-04-20 Intel Corporation Selectively processing different size data in multiplier and ALU paths in parallel
US6535948B1 (en) * 2000-05-31 2003-03-18 Agere Systems Inc. Serial interface unit
US7225320B2 (en) * 2000-12-28 2007-05-29 Koninklijke Philips Electronics N.V. Control architecture for a high-throughput multi-processor channel decoding system
CA2478571A1 (en) * 2001-03-02 2002-09-12 Atsana Semiconductor Corp. Apparatus for variable word length computing in an array processor
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
US8624906B2 (en) 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
US8725990B1 (en) 2004-11-15 2014-05-13 Nvidia Corporation Configurable SIMD engine with high, low and mixed precision modes
EP1883045A4 (en) * 2005-05-20 2016-10-05 Sony Corp SIGNAL PROCESSOR
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
WO2008010291A2 (fr) * 2006-07-21 2008-01-24 Fujitsu Limited Procédé et dispositif permettant de traiter des données liées à la variabilité dimensionnelle d'un système d'ordinateur simultané
US8532288B2 (en) * 2006-12-01 2013-09-10 International Business Machines Corporation Selectively isolating processor elements into subsets of processor elements
US8683126B2 (en) * 2007-07-30 2014-03-25 Nvidia Corporation Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US9064333B2 (en) 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8780123B2 (en) * 2007-12-17 2014-07-15 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8923385B2 (en) * 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US8681861B2 (en) * 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US8489851B2 (en) * 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
JP5568884B2 (ja) * 2009-04-02 2014-08-13 セイコーエプソン株式会社 映像処理装置、映像処理方法
GB2516288B (en) * 2013-07-18 2015-04-08 Imagination Tech Ltd Image processing system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602275A (en) * 1984-03-19 1986-07-22 Rca Corporation Television memory system
JPS63313979A (ja) * 1987-06-09 1988-12-22 Sony Corp ディジタルテレビジョン画像の動きを補償した補間方法
JPH01258184A (ja) * 1987-11-13 1989-10-16 Texas Instr Inc <Ti> 逐次ビデオプロセッサシステム
EP0444368A1 (en) * 1990-02-28 1991-09-04 Texas Instruments France Data input system for single-instruction multiple-data processor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8303536A (nl) * 1983-10-14 1985-05-01 Philips Nv Geintegreerde schakeling op grote schaal welke verdeeld is in isochrone gebieden, werkwijze voor het machinaal ontwerpen van zo een geintegreerde schakeling, en werkwijze voor het machinaal testen van zo een geintegreerde schakeling.
CA1258319A (en) * 1985-07-26 1989-08-08 Milton J. Kimmel Configurable parallel pipeline image processing system
US5249047A (en) * 1987-10-27 1993-09-28 Canon Kabushiki Kaisha Predictive coding system
US5130797A (en) * 1989-02-27 1992-07-14 Mitsubishi Denki Kabushiki Kaisha Digital signal processing system for parallel processing of subsampled data
CN1042282C (zh) * 1989-10-13 1999-02-24 德克萨斯仪器公司 用于同步矢量处理机的第二最近邻通讯网络、系统和方法
US5598545A (en) * 1989-10-13 1997-01-28 Texas Instruments Incorporated Circuitry and method for performing two operating instructions during a single clock in a processing device
US5187575A (en) * 1989-12-29 1993-02-16 Massachusetts Institute Of Technology Source adaptive television system
US5115309A (en) * 1990-09-10 1992-05-19 At&T Bell Laboratories Method and apparatus for dynamic channel bandwidth allocation among multiple parallel video coders
FR2692702A1 (fr) * 1992-06-17 1993-12-24 Philips Electronique Lab Dispositif de traitement de données ayant une architecture à instruction commune agissant sur des données multiples.
US5510842A (en) * 1994-05-04 1996-04-23 Matsushita Electric Corporation Of America Parallel architecture for a high definition television video decoder having multiple independent frame memories
JPH0877002A (ja) * 1994-08-31 1996-03-22 Sony Corp 並列プロセッサ装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602275A (en) * 1984-03-19 1986-07-22 Rca Corporation Television memory system
JPS63313979A (ja) * 1987-06-09 1988-12-22 Sony Corp ディジタルテレビジョン画像の動きを補償した補間方法
JPH01258184A (ja) * 1987-11-13 1989-10-16 Texas Instr Inc <Ti> 逐次ビデオプロセッサシステム
EP0444368A1 (en) * 1990-02-28 1991-09-04 Texas Instruments France Data input system for single-instruction multiple-data processor

Also Published As

Publication number Publication date
DE69519145D1 (de) 2000-11-23
EP0973100A1 (en) 2000-01-19
EP0701219B1 (en) 2000-10-18
EP0973101A1 (en) 2000-01-19
DE69519145T2 (de) 2001-04-05
US5850268A (en) 1998-12-15
EP0701219A1 (en) 1996-03-13
US5666169A (en) 1997-09-09
DE69526685D1 (de) 2002-06-13
EP0973101B1 (en) 2002-05-08
JPH0877002A (ja) 1996-03-22

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application