KR960008458B1 - Programmable divider - Google Patents

Programmable divider Download PDF

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Publication number
KR960008458B1
KR960008458B1 KR94003337A KR19940003337A KR960008458B1 KR 960008458 B1 KR960008458 B1 KR 960008458B1 KR 94003337 A KR94003337 A KR 94003337A KR 19940003337 A KR19940003337 A KR 19940003337A KR 960008458 B1 KR960008458 B1 KR 960008458B1
Authority
KR
South Korea
Prior art keywords
clock
outputs
stenb
ctlck
ctl
Prior art date
Application number
KR94003337A
Other languages
Korean (ko)
Other versions
KR950026122A (en
Inventor
Yong-Hoon Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to KR94003337A priority Critical patent/KR960008458B1/en
Publication of KR950026122A publication Critical patent/KR950026122A/en
Application granted granted Critical
Publication of KR960008458B1 publication Critical patent/KR960008458B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/02—Input circuits
    • H03K21/026—Input circuits comprising logic circuits

Abstract

a dividing controller (40) which outputs the initial data synchronized with state enable signal (STENB) by inputting dividing control data (DI) and outputs control signal (CTL); a clock selection part (20) which outputs clock control signal (CTLCK) according to CTL and STENB; a clock input part (10) which outputs the oscillating clock (FCK) inverted or not inverted according to CTLCK ; a counting part (30) which counts the data according to the output of the clock input part (10) by loading initial data; a divided clock generator (50) which generates state enable signal (STENB) and a divided clock (PCK) by inputting the output of the counting part (30).
KR94003337A 1994-02-24 1994-02-24 Programmable divider KR960008458B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR94003337A KR960008458B1 (en) 1994-02-24 1994-02-24 Programmable divider

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR94003337A KR960008458B1 (en) 1994-02-24 1994-02-24 Programmable divider

Publications (2)

Publication Number Publication Date
KR950026122A KR950026122A (en) 1995-09-18
KR960008458B1 true KR960008458B1 (en) 1996-06-26

Family

ID=19377691

Family Applications (1)

Application Number Title Priority Date Filing Date
KR94003337A KR960008458B1 (en) 1994-02-24 1994-02-24 Programmable divider

Country Status (1)

Country Link
KR (1) KR960008458B1 (en)

Also Published As

Publication number Publication date
KR950026122A (en) 1995-09-18

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