KR960006945Y1 - Pulse generator - Google Patents

Abstract

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Description

Pulse generator

1 is a block diagram of a pulse generator of the present invention

2 is a circuit diagram of the pulse generator of the present invention

3 is an output waveform diagram of each part of the pulse generator of the present invention

* Explanation of symbols for main parts of the drawings

1, 3: frequency divider 2: frequency multiplier

4: exclusive oar circuit PLL: phase lock

T-FF: Flip-flop

The present invention relates to a pulse generator, and more particularly, to a pulse generator capable of generating a phase pulse having an exact 90 ° phase difference with respect to an input pulse.

In general, the pulse signal from the pulse generator is used as the control signal in the case of the controller and as the carrier signal in the modulator. The conventional pulse generator used as described above does not generate pulses of the correct phase difference with respect to the input pulse. Since the error occurs due to the phase difference, the controller cannot perform an accurate control operation, and a demodulator cannot also perform an accurate demodulation operation.

Therefore, the present invention is intended to solve the above problems by generating a phase pulse having an exact 90 ° phase difference with respect to the input pulse.

Means for achieving the object of the present invention is the input pulse A frequency multiplier for multiplying the frequency distributed by the first frequency divider to a frequency of 2 ⁿ , and a frequency multiplied by the frequency multiplier. Generating a pulse having a late 90 ° phase by exclusively ORing a second frequency divider for generating in-phase pulses and generating in-phase pulses, an in-phase pulse output from the second frequency divider, and a frequency multiplied with the frequency multiplier. A secondary oar circuit is constructed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a block diagram of the pulse generator of the present invention, and FIG. 2 shows a detailed circuit diagram of the pulse generator of the present invention, and the frequency divider 1 shows an input pulse. The duty cycle is generated by a pulse with a duty cycle of 50%, which can be configured as a T flip-flop (T-FF) or a counter.

The frequency multiplier 2 is made from the frequency divider 1 Frequency multiplying pulse by 2 ⁿ times, where n is an integer and n> 0, it can be composed of a combination of a phase locker (PLL) and T flip-flop (CASCADE) or a counter, and when n = 0, bypass When n <0, it can be configured as a T flip-flop (T-FF) or a vertical connection of the counter. The frequency divider 3 receives the pulses produced by the frequency multiplier 2. It outputs in-phase pulse by dividing by. It also consists of T flip-flop or counter.

The exclusive oar circuit 4 generates an exclusive oarque (EX−-) by generating an exclusive phase of the phase pulse produced by the frequency divider 3 and the pulse generated by the frequency multiplier 2 to generate another phase pulse having a late 90 ° phase. OR).

Referring to the effect of the present invention configured as described above are as follows.

When an input pulse as shown in (a) of FIG. 3 is input to the first frequency divider 1, the input pulse is characterized by a T-FF, i.e., the next toggle signal. When it is inverted from high to low and from low to high, the pulse of the waveform as shown in (b) is outputted, and the pulse of (b) is a duty cycle D = 50%, It is a frequency-distributed pulse.

In the first frequency divider (1) The pulse of (b) divided by the frequency is input to the frequency multiplier (2) and outputs a pulse having a frequency multiplied by 2 ⁿ as shown in (c). In the above embodiment, since n = 2, the frequency multiplier configuration phase is fixed. The loop gain of the loop is 1, which has the same phase frequency as the input pulse.

In this way, the pulse of (c) output from the frequency multiplier 2 is input to the tee-flop constituting the second frequency divider 3 and inverted from high to low and low to high when the next toggle signal is input. In-phase pulses of the waveform as shown in (d) are output.

The exclusive pulse circuit 4 outputs an in-phase pulse as shown in (d) of FIG. 3 and an output waveform as shown in (C) of FIG. 3 output from the phase lock device (PLL) of the frequency multiplier (2). When applied to, other phase pulses can be obtained as shown in FIG.

Since the output phase pulse becomes a pulse 90 ° later than the in-phase pulse, a pulse having an accurate phase difference can be obtained.

As described above, the present invention uses the frequency divider, the frequency multiplier, the frequency divider, and the exclusive OR circuit so that the in-phase pulses accurately generate another phase pulse that is 90 ° later than the in-phase pulse. It is to provide an effect that can prevent the occurrence of errors due to the phase difference during control and double modulation by the pulse.

Claims (2)

(correction) Input pulse A first frequency divider (1) for frequency distribution by In the frequency divider A frequency multiplier 2 multiplied by a frequency 2 ^{n at a} frequency divided by A second frequency divider 3 for outputting a pulse multiplied by 2 ⁿ frequency in the frequency multiplier 2 as an in-phase pulse; And an exclusive oar circuit (4) for exclusively oaring the pulses input from the frequency divider (3) and the frequency multiplier (2). The method of claim 1. The frequency multiplier (2) is a pulse generator, characterized in that consisting of a phase locked loop and a counter.