KR960006702B1 - Contact resistance decreasing method of semiconductor device - Google Patents
Contact resistance decreasing method of semiconductor device Download PDFInfo
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- KR960006702B1 KR960006702B1 KR1019930004305A KR930004305A KR960006702B1 KR 960006702 B1 KR960006702 B1 KR 960006702B1 KR 1019930004305 A KR1019930004305 A KR 1019930004305A KR 930004305 A KR930004305 A KR 930004305A KR 960006702 B1 KR960006702 B1 KR 960006702B1
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- contact resistance
- semiconductor device
- high temperature
- tube
- reducing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
제 1도는 종래의 반도체 소자 콘택 저항 감소를 위한 공정도.1 is a process diagram for reducing a conventional semiconductor device contact resistance.
제 2도는 종래의 고온 일처러후의 실리콘 격자점과 이온 구조도.2 is a schematic diagram of silicon lattice points and ions after conventional high temperature treatment.
제 3도는 본 발명의 반도체 소자 콘택 저항감소를 위한 공정도.3 is a process chart for reducing the semiconductor device contact resistance of the present invention.
제 4도는 본 발명에 따른 실리콘 격자점과 이온 구조도.4 is a silicon lattice point and ion structure diagram according to the present invention.
제 5도는 종래의 본 발명의 캐리어 농도 비교도.5 is a carrier concentration comparison diagram of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 기판 2 : 필드산화막1 substrate 2 field oxide film
3 : 게이트산화막 4 : 폴리실리콘3: gate oxide film 4: polysilicon
5 : 층간절연막 6a, 6b : 소오스/드레인방법5 interlayer insulating film 6a, 6b source / drain method
본 발명은 반도체 소자의 콘택(Contact)저항 감소방법에 관한 것으로, 특히 튜브(Tube)로 저온에서 어닐링(Low Temperatura Annealing, LTA)하는 방법을 이용하여 이온 주입된 영역의 도판트(Dopant)를 완전히 활성화시켜 콘택 저항을 감소시키기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of reducing contact resistance of a semiconductor device. In particular, a dopant in an ion implanted region is completely removed by using a low temperatura annealing (LTA) method on a tube. To reduce contact resistance.
종래의 반도체 소자 콘택 저항 감소방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.A conventional semiconductor device contact resistance reduction method will be described below with reference to the accompanying drawings.
제 1도는 종래의 반도체 소자 콘택 저항 개선을 위한 공정도이고, 제 2도는 종래의 고온 일처리후 실리콘격자점과 이온구조도로써, 모스(MOS) 트랜지스터를 예를들면, 반도체 기판(1)에 필드산화막(2)을 성장하여 액티브 영역과 필드영역을 정의하고 게이트산화막(3), 폴리실리콘(4)등이 적층되어 게이트 전극을 형성하고 불순물 이온 주입으로 소오스/드레인 영역(6a,6b)을 형성한 다음 전면에 층간절연막(5)을 증착하여 소오스/드레인 영역(6a,6b)에 소오스/드레인 전극을 형성하기 위한 콘택을 혀엉한다.FIG. 1 is a process diagram for improving a conventional semiconductor device contact resistance, and FIG. 2 is a silicon lattice point and an ion structure diagram after a conventional high temperature work process, and a MOS transistor, for example, a field oxide film on a semiconductor substrate 1 (2) growing to define an active region and a field region, and a gate oxide film 3, polysilicon 4, etc. are stacked to form a gate electrode, and source / drain regions 6a and 6b are formed by impurity ion implantation. Next, an interlayer insulating film 5 is deposited on the entire surface to form contacts for forming source / drain electrodes in the source / drain regions 6a and 6b.
그리고 소오스/드레인전극이 형성된 부분에서 실리콘 기관과 메탈(Metal)이 접촉하여 이루어지는 콘택저항을 낮추어 스피드를 개선하기 위해, 제 1도(a)와 같이 전기적으로 전도역할을 하는 불순물을 첨가시키기 위해 콘택 영역에 이온 주입한다.In order to improve the speed by lowering the contact resistance formed by the contact between the silicon engine and the metal at the portion where the source / drain electrode is formed, the contact is added to add an impurity that electrically conducts as shown in FIG. Ion implantation into the area.
이때 사용하는 불순물은 실리콘 벌크(Bulk)를 깊이 침투하지 못하는 BF₂이온이다.At this time, the impurity used is BF₂ ion which does not penetrate deeply into silicon bulk.
그리고 제 1도(b)와 같이 고온 튜브에서 아주 짧은 시간동안 높은 온도에서 열처리 한다(일반적으로 950℃에서 1분 정도).And heat treatment at high temperature for a very short time in a high temperature tube as shown in Figure 1 (b) (typically 1 minute at 950 ℃).
그러면 이온 주입된 불순물이 충분히 활성화되지 못하고 활성화되는 속도보다 확산되는 속도가 훨씬 빨라서 결국 제 2도와 같은 형태가 되어 콘택 저항을 감소시킨다.Then, the implanted impurities are not sufficiently activated and the diffusion rate is much faster than the activation rate, resulting in the form of a second degree to reduce the contact resistance.
그러나 이와같은 종래의 콘택 저항 감소방법에 있어서는 하이 도스(high dose)로 이온 주입된 실리콘 영역을 고온 튜브에서 열처리하면 활성되는 속도보다 확산되는 속도가 횔씬 크므로 전기적으로 전도 역할을 콘택 부위의 캐리어 농도가 활성화되지 못하므로 콘택 저항이 높아지는 문제점이 있다.However, in the conventional method of reducing contact resistance, since the diffusion rate of the silicon region implanted at high dose in a high dose in a high temperature tube is much larger than the rate of activation, the carrier concentration of the contact portion is electrically conductive. There is a problem that the contact resistance is increased because is not activated.
본 발명은 이와같은 문제점을 해결하기 위하여 안출한 것으로써, 이온 주입과 고온 튜브에서의 열처리 공정사이에 저온 열처리하여 콘택 저항을 더욱 더 감소시켜 소자의 속도를 향상시키는데 그 목적이 있다.The present invention has been made to solve the above problems, and the object is to improve the speed of the device by further reducing the contact resistance by low temperature heat treatment between the ion implantation and the heat treatment process in the high temperature tube.
이와같은 목적을 달성하기 위한 본 발명을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다. 제 3도는 본 발명의 반도체 소자 콘택 저항 감소 공정도이고 제 4도는 본 발명에 다른 실리콘 격자점과 이온 구조도이고 제 5도는 종래와 본 발명의 캐리어 농도 비교도로써, 모스 트랜지스터를 예를들어 설명하면, 먼저 제 3도(a)와 같이 실리콘 기판(1)에 필드산화막(2)을 성장하고 게이트 산화막(3), 폴리실리콘(4)등이 적층된 게이트 전극을 형성하고 불순물 이온 주입으로 소오스/드레인 영역(6a,6b)을 형성한 다음, 전면에 층간절연막(5)을 증착하고 소오스/드레인 영역(6a,6b)에 소오스/드레인 전극을 형성하기 위한 콘택을 형성한다.Hereinafter, the present invention for achieving the above object will be described in detail with reference to the accompanying drawings. FIG. 3 is a process diagram for reducing contact resistance of a semiconductor device of the present invention, FIG. 4 is a structure diagram of silicon lattice points and ions different from the present invention, and FIG. 5 is a comparison chart of carrier concentrations between the conventional and the present invention. First, as shown in FIG. 3A, a field oxide film 2 is grown on the silicon substrate 1, and a gate electrode in which the gate oxide film 3, polysilicon 4, etc. are stacked is formed, and source / drain is implanted by impurity ion implantation. After the regions 6a and 6b are formed, an interlayer insulating film 5 is deposited on the entire surface, and contacts for forming source / drain electrodes are formed in the source / drain regions 6a and 6b.
그리고 실리콘 기판과 금속이 접촉할 부위의 콘택 저항을 감소시키기 위한 이온 주입을 실시한다(이때 사용하는 이온은 종래와 같이 BF₂이온을 사용한다).Then, ion implantation is performed to reduce the contact resistance at the site where the silicon substrate and the metal are in contact (the ions used at this time use BF 2 ions as in the prior art).
그리고 제 3도 (b)와 같이 저온(600℃ 정도)에서 30∼60분 정도 어닐링하는 LTA 공정을 실시한다.Then, as shown in FIG. 3 (b), the LTA process is annealed for about 30 to 60 minutes at low temperature (about 600 ° C).
이때 LTA 공정동안 이온 주입된 불순물은 확산되는 속도보다 활성화되는 속도가 더크므로 결국 제 4도와 같이 실리콘 격자점에 위치한다.At this time, since the impurity implanted during the LTA process is activated faster than the diffusion rate, it is finally located at the silicon lattice point as shown in FIG.
그후 제 3도 (c)와 같이 높은 튜브에서 짧은 시간동안 고온으로 어닐링한다(950℃정도에서 10분간).Then anneal to high temperature for a short time in a high tube as shown in Figure 3 (c) (about 10 minutes at 950 ℃).
고온에서 짧은 시간동안 일처리하면, 실리콘 표면의 불순물 농도가 증가되므로 전도 역할을 하는 캐리어가 증가하여 콘택 저항을 낮춘다.After a short period of time at high temperatures, the concentration of impurities on the surface of the silicon increases, resulting in an increase in carriers that serve as conduction, thereby lowering contact resistance.
이상에서 설명한 바와같이 본 발명의 콘택 저항 감소방법에 있어서는 이온 주입된 불순물을 완전히 활성화시키므로써 실리콘 표면의 불순물 농도가 증가되어 콘택 저항이 감소됨과 더불어 반도체 소자의 속도가향상되며, 또한 실리콘 뒷면의 디팩트(Defect)를 형성하는 층을 만들어 알칼리 금속을 포획하는 인터널(internal)게터링 역할을 함으로써 액티브 영역의 디팩트 덴서티(Defect Density)를 감소시켜 소자의 성능을 향상시키는 효과가 있다.As described above, in the method of reducing the contact resistance of the present invention, by fully activating the ion implanted impurities, the concentration of impurities on the silicon surface is increased, thereby reducing the contact resistance and increasing the speed of the semiconductor device. By forming a layer forming a defect and acting as an internal gettering trapping alkali metal, the defect density of the active region is reduced, thereby improving the performance of the device.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930004305A KR960006702B1 (en) | 1993-03-19 | 1993-03-19 | Contact resistance decreasing method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019930004305A KR960006702B1 (en) | 1993-03-19 | 1993-03-19 | Contact resistance decreasing method of semiconductor device |
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| KR940022701A KR940022701A (en) | 1994-10-21 |
| KR960006702B1 true KR960006702B1 (en) | 1996-05-22 |
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| KR1019930004305A KR960006702B1 (en) | 1993-03-19 | 1993-03-19 | Contact resistance decreasing method of semiconductor device |
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