KR960006273B1 - Address input device of semiconductor memory element - Google Patents

Abstract

an address buffer means which receives the address signal from the external; an address signal generating means which generates inner address signal which is reduced or increased from the addresses outputted from the address buffer means; an address transition detecting means which senses the variation of the address signal outputted from the address buffer means; a multiplex means which selectively outputs output signal from the address signal generating means; an address latch means which latches output signal from the multiplex means during necessary time; a control means which controls the operation of the address buffer means, the address signal generating means, the multiplex means and the address latch means by the address transition detecting means and /RAS, /CAS signal.

Description

Address input device of semiconductor memory device

1 is a block diagram of an address input device according to the prior art.

2 is a timing diagram of signals associated with the operation of FIG.

3 is a block diagram of an admittance input device according to an embodiment of the present invention.

FIG. 4 is a detailed circuit diagram of the address input device shown in FIG.

5 is an operation timing diagram of FIGS. 3 to 4 when there is no change in the input address.

6 is an operation timing diagram of FIGS. 3 to 4 when there is a change in input address.

* Explanation of symbols for the main parts of the drawings

11, 21: address buffer section 12, 22: address latch circuit section

13,23: control circuit section 14,24: address signal generation circuit section

25 dress transition detection circuit section 26 multiplex circuit section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address input device of a semiconductor memory device. In particular, an address transition detector for detecting a change in an input address signal is implemented in the address input device, and an output address inputted from the outside of the device is output. If there is no signal change, the semiconductor memory device operates in nibble mode by transferring the address signal output from the internal address signal generating circuit to the internal circuit, and there is a change in the address signal input from the outside of the device. The present invention relates to an address input device which transfers an address signal input from the outside to an internal circuit so that the semiconductor memory device operates in a page mode.

In order to operate DRAM Dynamic Random Access Memory (DRAM) devices, it takes a lot of time to sense the data stored in the cell because of the characteristics of the cell. After selecting one word line and sensing data of all cells connected to the word line in a bit line sense amplifier, only the column address is changed to sense the sensed. A method of outputting cell data of a data bit line selected by a column address among data is widely used.

One of these methods, nibble mode, accepts the column address when the / CAS (Column Addres Strobe) signal transitions to the active state, and then changes the external address signal every time the / CAS signal changes to the active state. Irrespective of the above, the data of the data bit line selected by the internal address signal output from the internal address signal generation circuit is output.

Referring to the block diagram of FIG. 1 and the timing diagram of FIG. 2, a configuration and operation of a column address input device implementing the conventional nibble mode will be described.

The column address input device implementing the conventional nibble mode includes an address buffer 11 for receiving an address signal from the outside of the device, an address latch circuit portion 12 for latching the input address signal, In the first / CAS cycle after the / RAS (Row Address Strobe) signal transitions to the active state, the address signal input from the outside of the device is transferred to the device, and from the second cycle in which the / CAS signal transitions to the active state, the internal address is The control circuit 13 which transfers the signal output from the signal generation circuit section 14 to the internal circuit, and the address signal which stores the address input by the first / CAS signal and outputs the internal address signal from the second / CAS cycle. It consists of the generation circuit part 14.

First of all, when the address buffer part enable signal ENABLE is enabled at time t1 before the / CAS signal transitions to the active state, the address buffer part 11 operates so that the address signal ADD input from the outside of the device is internal to the device. The address signal is transmitted to the AY line which is in standby state.

After that, when the address latch signal LATCH is enabled at a time point t2, the address latch circuit portion 12 latches the address signal A1 inputted through the address buffer section 11 at that time, and in the case of latching the address signal, the input AY line. The address signal of AY2, which is the output of the address latch circuit section 12, remains unchanged even after the address of the address is changed. After the address is latched, the address buffer enable signal ENABLE transitions to the standby state. .

The address signal thus produced becomes the address signal AYi in the element and is transferred to the column decoder to select the data bit line, and the address signal AYi is input to the address signal generation circuit section 14.

When the / CAS signal, which remained in the active state, transitions back to the precharge mode at the time t3, the signal INC is enabled to bust the output signal BY of the address signal generation circuit unit 14 from address A1 to A2.

After that, when the signal CLA for selecting whether to transfer the address signal input to the address buffer section 11 to the internal path or the address signal output from the internal address signal generation circuit section 14 to the internal circuit is inputted, The address signal A2 of the output terminal BY of the address signal generation circuit portion 14 is transferred to the address line AYi in the element.

After that, whenever the / CAS signal is changed to the precharge mode (time t5), the INC signal that can change the address signal of the address signal generation circuit unit 14 is enabled, and the address signal is generated by the enabled INC signal. The output signal BY of the unit 14 is changed to control the operation of the device internal circuit.

The conventional address input device in the nibble mode operating as described above uses only a limited number of addresses output from the inside of the device (four in the normal nibble mode). It is difficult to accept a word line with the enabled word line. If one word line is continuously receiving the next address signal and wants to accept an irregular new address signal, the word line is again enabled. There is a problem such as.

Therefore, the present invention solves the limitation of the number of addresses generated inside the device, which is a problem in the conventional address input device, and the address force for continuously receiving an arbitrary address signal while the word line is enabled. It is an object to provide a device.

In order to achieve the above object, the address input device of the present invention includes an address buffer means for receiving an address signal from the outside of an element and an address for generating an internal address signal which is sequentially increased or decreased from an address output from the address buffer means. Multiplexing means for selectively outputting a signal generating means, an address transition detection number for detecting a change in an address signal output from only the address buffer number, and an output signal from the address buffer means or an output signal from the address signal generating means; Address latch means for latching the output signal from the multiplex means for a necessary time; the address buffer means, the address signal generating means, and the multiplex by means of the address transition detecting means and the rasva and casba signals; And control means for controlling the operation of the device, the address raecheo means were provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

3 is a block diagram of an address input apparatus according to an embodiment of the present invention, in which address buffer 21 for receiving an address signal from the outside of the device and address output from the address buffer 21 are sequentially formed. An address signal generation circuit section 24 for generating an internal address signal that is increased or decreased, an address transition detection loop section 25 for detecting a change in the address signal output from the address buffer section 21, and the address buffer section; A multiplex circuit section 26 for selectively outputting an output signal from (2l) or an output signal from the address signal generating circuit section 24, and latching the output signal from the multiplex circuit section 26 for a necessary time. The address latch circuit section 22 and the address transition detection circuit section 25, the ras bar (/ RAS) and the cas bar (/ CAS) signals Is composed of a buffer-less portion 21, the address signal generating circuit 24, a multiplex circuit 25, the address control circuit 23 for controlling the operation of the latch circuit 22.

4 shows a detailed circuit diagram of the address input device shown in FIG.

The control circuit unit 23 inverts the input casbar (/ CAS) signal and outputs it to the first node N1 and the second node by delaying the input / ras // RAS signal for a predetermined time. A delay circuit for outputting to the N2, a NOR gate G2 for NOR operation of the casbar signal and the signal of the second node N2, and outputting to the third node N3, and the first node A NAND gate G3 for NAND operation of the Nl and the third node B3 and outputting the fourth node N4 is connected between the fourth node N4 and the fifth node N5. Delayed inverter G4 and the inverter G5 connected between the fifth node N5 and the sixth node N6, and the delay connected between the sixth node N6 and the seventh node N7. A ninth node by NAND operation on the circuit, the inverter G6 connected between the seventh node N7 and the eighth node N8, and the signals of the sixth node N6 and the eighth node N8. An output signal of the NAND gate G7 output to N9 and the address transition detection circuit 25; NOR operation (N36) to NOR operation (G8) for outputting to the first node (N10), and NAND operation for the ninth node (N9) and the eleventh node (Nl1) to output to the twelfth node (N12) NAND gate G9 and a NAND gate G10 outputting the twelfth node Nl2, the tenth node Nl0, and the third node N3 to the eleventh node N11 by NAND operation. do.

The address buffer unit 21 performs a NAND operation on the third node N3 and the address add (n) to output the NAND gate G11 to the thirteenth node N13, and the thirteenth node ( An inverter G12 connected between the N13 and the first node N14.

The address signal generation circuit part 24 is connected between the inverter G21 connected between the fourteenth node Nl4 and the twenty-fourth node N24, and the third node N3 and the twenty-first node N21. The inverter G18, the NAND gate G19 for outputting the NAND operation signal of the 21st node N21 and the address (INC) signal to the 22nd node N22, the 22nd node N22 and The inverter G20 connected between the 23rd node N23 and the 22nd node N22 and the 23rd node N23 transfer the synchronism of the 24th node N24 to the 25th node N25. To the transfer gates MP1 and MN1, the inverter G22 which inverts the address signal INC and outputs it to the thirtieth node N30, and to the signals of the address signal INC and the thirtieth node N30. Transfer gates MP2 and MN2 for transmitting the signal of FIG. 29 (N29) to the 25th node N25, and an inverter G23 connected in parallel between the 25th node N25 and the 26th node N26. G24 and the address signal INC and the thirtieth node N30 Inverters connected in parallel between the transfer gates MP3 and MN3 for transmitting signals of the 26th node N26 to the 27th node N27 by the synth and the 27th node N27 and the 28th node N28 And an inverter G27 connected between the G28 and G26 and the 28th node N28 and the 29th node N28.

In addition, the multiplex circuit unit 26 is connected between the inverter G13 connected between the third node N3 and the sixteenth node N16, and between the fourteenth node N14 and the fifteenth node N15. An NMOS transistor MN4 connected to the sixteenth node N16 and a gate connected to the fifteenth node N15 and the thirty-nine node N29, and a gate connected to the third node N3. NMOS transistor MN5.

The address latch circuit 22 may NOR a signal of the inverter G16 connected between the fifth node N5 and the nineteenth node N19, and the signals of the fifteenth node 15 and the twentieth node N20. NOR for calculating and outputting the NOR gate G14 for outputting to the 17th node N17 and the synchronism of the 17th node N17 and the 19th node N19 for NOR operation and for outputting to the 20th node N20. An inverter G15 connected between the gate G17 and the seventeenth node N7 and the eighteenth node N18.

The address transition detection circuit unit 25 is connected in series between the inverter G28 connected between the fourteenth node N14 and the thirty first node N31, and the thirty-first node N31 and the thirty-second node N32. NAND gate G31 for NAND operation of the connected inverters G29 and G30, the signals of the fourteenth node N14 and the thirty-second node N32, and outputting the signals to the thirty-third node N33; The inverters G32 to G34 connected in series between the N31 and the 34th node N34, and the synths of the 31st node N31 and the 34th node N34 are NAND-calculated to the 35th node N35. NAND gate G35 for outputting the signal of the 33rd node N33 and the 35th node N35 and NAND gate G36 which outputs to the input of the NOR gate G8 of the control circuit 23. It is composed of

First, the operation by the above configuration will be briefly described. When there is no bust of an address signal input from the outside, an address is generated internally to a change of a casing signal so that a continuous change can be made using this address. When there is a change in the address signal input from the outside, an address signal input from the outside is transferred to the inside of the device in response to the continuous change of the CAS signal to perform the operation.

Then, referring to the operation of FIGS. 3 to 4 when there is no change in the address signal input from the outside of the device with reference to the signal timing diagram shown in FIG. 5, the / CAS signal transitions to the active state. When the address buffer enable signal ENABLE is enabled at a time point t1 before, the address buffer 21 is operated so that the address signal A1 outside the device is transferred to the inside of the device and placed on the standby line AY.

In this case, the signal CLA for determining whether to transmit an externally input address signal to the device or to transmit an internally generated address signal to the device maintains a high level state by detecting a change in the address. The admitted signal is transmitted to the inside of the device via the control circuit unit 23.

After that, when the address latch signal LATCH is enabled at time point t2, the address latch circuit 22 latches the address signal A1 input at that time. It stays the same.

The address signal thus produced is transferred to the address line AYi inside the device, and is passed to the internal address signal AYi column decoder and used to select the data bit line.

Then, when the / CAS signal transitions to the precharge mode at time t3, an INC signal that can change the address signal of the address signal generation circuit portion 24 is enabled, and the address signal generation circuit portion 24 is enabled by this INC signal. Is operated to output the internal address signal A2 to the output BY, and at this time, the CLA signal that determines whether to input an externally input address signal into the device or to input an internally generated address signal into the device is The internal address signal A2 outputted to the output BY of the internal address signal generation circuit unit 24 is transferred to the address line AYi in the device.

After that, when the / CAS signal changes to the precharge mode in the state where there is no change in the address signal inputted from the pseudonym, the INC signal that can thrive the address signal of the address signal generating circuit 24 is enabled, and the INC signal is enabled. The ad signal generator 24 operates to output the changed address signal to the output BY, thereby controlling the operation of the internal circuit.

Referring to the operation of FIGS. 3 to 4 when there is a change in the address input from the outside of the device with reference to the signal timing diagram shown in FIG. 6, the address at time t1 before the / CAS signal transitions to the active counterpart When the buffer part enable signal ENABLE is enabled, the address buffer part 21 operates so that the address signal A1 of the part of the device is transferred to the inside of the device and placed on the standby line AY.

At this time, the signal CLA for determining whether to transmit an externally input address signal to the device or to transmit an internally generated address signal to the device maintains a high level state by detecting a change in the address. The address signal is transferred into the device via the control circuit 23.

After that, when the address latch signal LATCH is enabled at the time point t2, the address latch circuit section 22 latches the address signal A1 input at that time. It stays the same.

The address signal thus produced is transferred to the address line AYi in the element, and the internal address signal AYi is sent to the column decoder to select the data bit line, and this address signal AYi is input to the address signal generation circuit section 24.

In the case where there is a change in the address signal input from the outside of the element after latching the address signal input from the address latch circuit section 22, if the number of addresses has latched the address and before the latch state is released, When the CLA signal is generated at the TLA, the CLA signal is kept at a high level so that an external address signal is transmitted to the internal address line Ayi until the hour hand t5.

On the other hand, when the change of the address signal occurs after the latch state is released, the INC signal capable of changing the address signal of the address signal generation circuit section 24 is included when the / CAS signal is changed to the precharge mode at the correct time t3. In response to this INC signal, the output BY of the address signal generation circuit portion 24 is changed from A1 to B1, and at this time, the CLA signal is changed to a low level state that receives an internally generated address signal. The address signal B1 of the output BY of 24 is transmitted to the address line AYi inside the element.

After that, when the input address signal changes again, the CLA signal transitions back to a high level state so that an address signal input from the outside of the device is input into the device, and the address signal input from the outside of the device is transferred to the address line AYi inside the device. Will be delivered.

When there is no change in the input address thereafter, as shown in FIG. 2, whenever the / CAS signal changes to the precharge mode, an INC signal capable of changing the address signal of the address signal generator 24 is inputted. As a result, the output BY of the address signal generating circuit section 24 is changed so that the inside of the device is controlled by these signals. When there is a change in the input address, the CLA signal becomes a high level state as shown in FIG. Instead of the output of the signal generating circuit section 24, an external input address signal is transferred to the internal address line AYi.

As described above, when the address input device according to the present invention is used inside the semiconductor memory device, if there is no change in the address signal input from the outside of the device, the address input device outputs the data using the address signal output from the internal address signal generation circuit. When the data is selected and there is a change in the address signal input from the outside of the device, the selected data can be outputted by the changed address signal, so that it is easy to store the data in a cell corresponding to the continuous address signal. It is possible to expect a fast operation speed, it is possible to change from the generation of the continuous address signal to the irregular address signal, there is an effect that can be used alternately the generation of the continuous address signal and the generation of the irregular address signal.

The hatched portions in the signal timing diagrams of FIGS. 2, 5, and 6 indicate a don't care state that has no effect on the operation of the circuit, regardless of the state of the signal. It is.

Claims (1)

Address buffer means for receiving an address signal from the outside of the element, address signal generating means for generating an internal address signal that is sequentially increased or decreased from an address output from the address buffer means, and an address signal output from the address buffer means An address transition detecting means for detecting a change in the signal, a multiplexing means for selectively outputting an output signal from said address buffer means and an output signal from said address signal generating means, and a time required for output signal from said multiplexing means; A control number for controlling the operation of the address buffer means, the address signal generating means, the multiplexing means, and the address latching means, respectively, by the address latch means for latching during An address input unit of the semiconductor memory device comprising a.