KR0144404B1 - Regulator apparatus of burst length - Google Patents

Abstract

The present invention relates to an apparatus for adjusting a burst length, by inputting the first address signal and the last address signal through two input terminals to compare the consecutively generated address signals with the last address signal so as to interrupt the burst operation. And a circuit for stopping the burst operation when the last address signal becomes zero by inputting the first address signal and the last address signal to two input terminals so that the last address signal is decremented by the counter circuit one by one. It relates to a burst length adjusting device.

Description

Burst Length Adjuster

1 is a circuit address related circuit diagram in which a conventional burst operation is possible.

2 is a circuit diagram showing a first embodiment of a burst length adjusting device according to the present invention.

3 is a circuit diagram showing a second embodiment of the burst length adjusting device according to the present invention.

* Explanation of symbols for main parts of the drawings

101: internal address generating circuit portion 201: address register portion

202, 302: comparator 301: counter circuit

The present invention inputs the first address signal and the last address signal during the operation of a dynamic random access memory (DRAM) and continuously accesses (reads / writes) data for the addresses therebetween without changing external signals. It relates to a [burst length] adjusting device implemented to be possible.

1 is a circuit diagram related to a column address capable of a conventional buster operation, and includes an input / output terminal for inputting / outputting an address, and an internal address generating circuit unit 101 for generating a continuous internal address from an address inputted to the input terminal. And a multiplex circuit unit for switching an address input from the input terminal and an internal address signal generated from the internal address generation circuit unit to be transferred to the output terminal.

When one address is input from the input terminal, the signal is logically combined with an address input buffer enable signal and transmitted to the output line n1 of the logic gate G1. The address signal transmitted to the node N1 is transmitted to the input terminal. Since the address signal inputted as is an inverted signal, the address signal inputted from the input terminal is transferred to the output terminal through the inverter G2 connected between the node N1 and the node N2.

On the other hand, the address signal input to the input terminal is transferred from the transfer transistor Q1 to the node N12 of the internal address generation circuit unit 101 by the control signal set1.

The internal address generator circuit 101 is connected between the input signal [bn-1: clock signal clk] line N9 and node N10 and transmits the signal of node N11 to node N12. An inverter G4 connected between a transfer transistor Q2, the node N9 and the node N10, and an inverter G6 connected between the node N12 'and the node N13. A transfer transistor Q3 connected between the node N10 and the node N9 and transmitting a signal of the node N14 to the node N12, the node N9, and the node N10. A total desorption transistor Q4 connected between the node N13 and a node N15, an inverter G7 connected between the node N15 and the node N16, and the note N16. And a transfer transistor connected between an inverter G8 and the node N9 and the node N10 and transferring a signal of the node N17 to the node N15. Q5) and, An inverter G10 connected between the node N16 and the node N11 and an inverter G9 connected between the node N16 and the node N18 are provided.

If the address signal input from the node N12 of the internal address generation circuit unit 101 is 'high', the node N13 becomes low. When the input signal clk of the internal address generator circuit is changed to low, the transfer transistor Q4 is operated to transfer the address signal of the node N13 to the node N15, so that the node N15 is low, The node N16 is high and the node N18 is low. On the other hand, when the input signal clk is in a low state, the transfer transistor Q3 operates to store the signal of the node N13 through the inverters G5 and G6 so that the next input signal clk is changed. The current signal is maintained until. Thus, the inverters G5 and G6 serve as one memory cell.

The signal of the node N16 is fed back to the node N11 through the inverter G10. When the input signal clk is changed from low to high, the transfer transistor Q2 is operated to transfer the signal of the node N11 to the node N12. Therefore, the node N12 is turned low and the node N13 is turned high. Meanwhile, since the input signal clk is in a high state, the transfer transistor Q5 operates to store the signal of the node N16 through the inverters G7 and G8. Accordingly, the inverters G7 and G8 serve as memory cells, and keep the node N16 high and the node N18 low until the next input signal clk is changed.

When the input signal clk is changed from high to low from the input line N9, the transfer transistor Q4 is operated to transfer the signal of the node N16 stored in the memory cell to the node N15. Will be given. Accordingly, the node N15 goes from low to high, and the node N16 goes low to make the output node N18 of the internal address generation circuit unit 101 high.

Accordingly, the internal address generator circuit 101 counters one address signal input from the input terminal when the input signal clk is changed from high to low.

The signal of the node N2 input from the input terminal from the multiplex circuit and the signal of the output line N18 from the internal address generating circuit unit 101 are switched and transferred to an output terminal to thereby output an internal address signal (yadd). -int).

In the conventional DRAM, in the case of a synchronous DRAM, a function of inputting one address, generating a continuous internal address from the address, and reading or writing column data according to the address is provided. Have. However, in the conventional method as described above, the length of performing the burst is several ways, that is, 1, 2, 4, 8,... Etc., but arbitrary burst operation is impossible.

For the random burst operation, the column address is generated from the input address to the full page method and the operation is completed at a certain point. For this operation, the burst end signal is input by keeping a specific time. After the inside of the device stops operating, another operation proceeds. In this operation, the external signal of the device is busy because the outside of the device inputs a signal to stop the burst operation and then another operation signal. That is, the timing of the signal input from the outside of the device becomes critical.

On the other hand, in case of using a fixed burst wrench, the length of an address to be made from an externally input address is not always constant, which causes a problem in that it is difficult to cope with an input address having an arbitrary length.

Accordingly, the present invention provides a burst length adjusting device capable of inputting the first address signal and the last address signal when an arbitrary column address is input and continuously accessing data on the addresses without changing an external signal therebetween. The purpose is.

In order to achieve the above object, in the present invention, the first address signal and the last address signal are input to two input terminals so that the burst operation is stopped when the consecutively generated address signals are the same as those of the last address signal. In addition, by inputting the first address signal and the last address signal to the two input terminals, the circuit is configured to emphasize the burst operation when the last address signal becomes zero by decreasing the last address signal by one by the counter circuit. Implemented.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in more detail.

2 is a circuit diagram showing a first embodiment of a burst length adjusting device according to the present invention, which includes an input terminal for inputting an address, an output terminal for outputting an internal address, and a continuous internal input from the address inputted to the input terminal. An internal address generating circuit portion 101 for generating an address, a multiplex circuit portion for switching an address input from the input terminal and an internal address signal generated from the internal address generating circuit to transfer to an output terminal, and an input from the input terminal An address register section 202 for receiving and storing the last address signal of the first address, and an output signal of the internal address generating circuit section and the address register section for comparing the output signals of the address register section 202 to produce a signal for stopping the burst operation in the same case. ).

Since the address generation circuit section and the multiplex circuit section are the same as those of the conventional ones in the configuration and operation thereof, they will be briefly described here.

When one address signal is input from the input terminal, the internal address issuing circuit unit 101 generates a continuous internal address from the input address. The multiplex circuit unit switches an address input to the input terminal and an internal address signal generated from the internal address generation circuit unit and transfers it to an output terminal.

The address register section 201 is connected between the node N19 and the node N21, and transfer transistor Q8 and the node N19 and the node for transmitting a signal of the address line N21 to the node N22. Inverter G12 connected between N20, inverter G13 connected between node N22 and node N23, and inverter G24 connected between node N23 and node N24. It is composed of

The address register unit 201 inputs the last address signal of the first input address signal from the input terminal. When the address signal enters the address line N21, the transfer transistor Q8 operates by the control signal set2 to transfer the signal of the node N21 to the node N22. The address signal transmitted to the node N23 is stored in a memory cell composed of inverters G13 and G14 configured in parallel and output to the output line N24 through the inverter G15.

The comparator 202 is provided with a NAND gate G16 and a NOR gate G17 which input the output signal N18 of the internal address generation circuit portion and the output signal N24 of the address register portion 201, and the NAND. NAND gate G19 which receives the output signal N25 of the gate G16 and the signal N27 in which the output signal of the NOR gate NG17 is inverted, and the output signal N28 of the NAND gate G19 And an inverter G21 connected between a NAND gate G20 for inputting control signals d1-d3, an output line of the NAND gate G20, and a node N33, and a signal of the node N33. It consists of an output terminal (bst_end).

The comparator 202 compares an output signal from the internal address generation circuit unit 101 and an input signal input to the address register unit 201 so as to output a signal bst_end which interrupts the burst operation in the same case. do.

That is, when the output signal N18 continuously generated from the address signal input to the internal address generation circuit unit 101 and the last address signal N24 of the first address signal input to the address register unit 201 are the same. The output node N32 of the NAND gate G19 is made high, and if it is different, the output node N32 of the NAND gate G19 is made low.

When the node N28 is high, the output signal bst_end becomes high to stop the burst operation. When the node N28 is low, the output signal bst_end becomes low and the internal address is lost. The generation circuit unit 101 continuously creates an internal address until the output signal bst_end becomes high. The output signal bst_end for controlling the burst operation is determined in logical combination with the control signals d1-d3 according to the potential state of the node N28.

Accordingly, the burst length adjusting device according to the first embodiment of the present invention inputs a column address corresponding to the last burst before the continuous data access from which the address signal is input from the input terminal occurs or during the burst operation. Let's do it. The input last column address is stored in the address register and compared with the column address generated in the internal address generator. The column address generated in the internal address generator is a burst end address. If so, the burst operation is stopped.

Fig. 3 is a circuit diagram showing a second embodiment of the burst length adjusting device according to the present invention, comprising: an input terminal for inputting an address, an output terminal for outputting an internal address, and a continuous internal from the address inputted to the two-wall terminal; An internal address generating circuit portion 101 for generating an address, a multiplex circuit portion for switching an address input from the input terminal and an internal address signal generated from the internal address generating circuit portion to be transferred to the output terminal, and from the input terminal A counter circuit unit for inputting the last address signal of the inputted first address and reducing the input address signal by one by a clock signal input periodically, and comparing the output signal from the counter circuit unit to transfer the output signal to the output terminal; Comparator 302 is provided.

Since the address generation circuit section and the multiplex circuit section are the same in their construction and operation as those of the first and the first embodiments of the present invention, they will be briefly described here.

When one address signal is input from the input terminal, the internal address generation circuit unit 101 generates a continuous internal address from the input address. The multiplex circuit part exchanges an address input from the input terminal and an internal address signal generated from the internal address generator circuit to be transferred to an output terminal.

The counter circuit 301 is connected between the input signal [= clock signal clk] line N37 and the node N38, and transfer transistor Q10 for transmitting the signal of the node N39 to the node N40. And an inverter G23 connected between the node N37 and the node N38, an inverter G24 connected between the node N40 and a node N41, the node N41 and a node. An inverter G25 connected between the N42, a transfer transistor Q11 connected between the node N38 and the node N37, and transmitting a signal of the node N42 to the node N40; A transfer transistor Q12 connected between the node N37 and the node N38 and transferring a signal of the node N41 to the node N43, and between the node N43 and the node N44. The connected inverter G26, the inverter G27 connected between the node N44 and the node N45, the node N37 and the node N38 are connected, and the signal of the node N45. To A transfer transistor Q13 for transmitting to the node N43, an inverter G28 connected between the node N44 and the node N46, and a node connected between the node N44 and the node N39. An inverter G29 is provided.

If the address signal input from the node N40 of the counter circuit unit 301 is 'high', the node N41 becomes low. When the input signal clk of the internal address generator circuit is changed to low, the transfer transistor Q12 operates to transfer the address signal of the node N41 to the node N43, so that the node N43 is low, The node N44 is high and the node N46 is low. On the other hand, when the input signal clk is in a low state, the transfer transistor Q11 operates to store the signal of the node N41 through the inverters G25 and G24 so that the next input signal clk is changed. The current signal is maintained until. Thus, the inverters G25 and G24 serve as one memory cell.

The signal of the node N44 is fed back to the node N39 through the inverter G29. When the input signal clk is changed from low to high, the transfer transistor Q10 operates to transfer the signal of the node N39 to the node N40. Therefore, the node N40 is turned low and the node N41 is turned high. Meanwhile, since the input signal clk is in a high state, the transfer transistor Q13 operates to store the signal of the node N44 through the inverters G27 and G26. Accordingly, the inverters G27 and G26 serve as memory cells, and keep the node N44 high and the node N46 low until the next input signal clk is changed.

When the input signal clk is changed from high to low from the input line N37, the transfer transistor Q12 is operated to transfer the signal of the node N44 stored in the memory cell to the node N43. Will be given. Accordingly, the node N43 changes from low to high and the node N44 goes low to make the output node N46 of the counter circuit 301 high.

Accordingly, the counter circuit unit 301 counters one address signal input from the input terminal when the input signal clk is changed from high to low. That is, every one period in which the input signal clk is changed from high to low, an address signal of half a period is generated to output an output signal of which the input address signal is reduced by one.

The comparator 302 includes a NOR gate G30 for inputting an output line N46 and a control signal c1-c3 of the counter circuit unit, and an output terminal bst_end for outputting an output signal of the NOR gate G30. It is provided.

When the output signal output from the counter circuit unit 301 reaches a certain signal (zero: 0), the comparator 302 turns all of the input signals of the NOR gate G30 to low to output the output signal bst_end. High to stop the burst operation.

When the burst length adjusting device of the present invention described above is implemented in the semiconductor device, when an arbitrary column address is input, the first address signal and the last address signal are inputted, and data for the addresses therebetween is converted into an external signal. There is an effect that can be accessed continuously without change.

Claims (4)

An input terminal for inputting an address signal, an output terminal for outputting an internal address signal, internal address generating means for generating a continuous internal address from the address signal inputted to the input terminal, and an address signal inputted to the input terminal And multiplexing means for switching an internal address signal generated from said internal address generating means and transferring it to said output terminal, an address register means for storing a last address signal of an address input from said input terminal, and generating said internal address; And means for comparing the output signal from the address register means and a control signal to produce a signal which stops the burst operation in the same case. The apparatus of claim 1, wherein the last column address signal input to the address register means can be input after inputting a column address signal from the input terminal or during a burst operation. An input terminal for inputting an address signal, an output terminal for outputting an internal address signal, internal address generating means for generating a continuous internal address from the address signal inputted to the input terminal, and an address signal inputted to the input terminal And the multiplexing means for switching an internal address signal generated from the internal address generating means and transferring the internal address signal to the output terminal, and a clock signal periodically inputted by inputting the last address signal of the address inputted from the input terminal. And counter means for reducing the received address signal one by one, and comparing means for outputting a signal for stopping the burst operation when all the signals are zero by comparing the output signal and the control signal from the counter means. Burst This adjustment. 4. An apparatus according to claim 3, wherein said comparing means comprises a NOR gate.