KR100768455B1 - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device which eliminates waste of information amount and reduces power consumption. Registers 12 and 15 for holding the first information and information generating circuits 11 and 14 for receiving the first signal from the outside and generating the second information, wherein the first signal is used for the first information. A signal indicating inversion, wherein the information generation circuit is a semiconductor device that generates the second information based on the first information and the first signal.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

1 illustrates a first principle of the present invention.

2 is a block diagram showing one embodiment of the present invention;

3 is a block diagram showing a first embodiment of a data input unit provided in a memory;

4 is a timing diagram illustrating the circuit operation of FIG. 3;

Fig. 5 is a block diagram showing an embodiment of an address input unit provided in a memory.

Fig. 6 is a block diagram showing a second embodiment of the data input unit provided in the memory.

7 is a timing diagram illustrating the circuit operation of FIG. 6.

FIG. 8 is a circuit diagram showing an example of the configuration of an input latch portion shown in FIG. 6. FIG.

Fig. 9 is a block diagram showing a third embodiment of the data input unit provided in the memory.

10 is a timing diagram showing the circuit operation of FIG. 9;

Fig. 11 is a block diagram showing the fourth embodiment of the data input unit provided in the memory.

12 is a timing diagram illustrating the circuit operation of FIG. 11.

Fig. 13 is a block diagram showing the fifth embodiment of the data input unit provided in the memory.

14 is a timing diagram illustrating the circuit operation of FIG. 13.                 

Fig. 15 is a block diagram showing the fifth embodiment of the data input unit provided in the memory.

16 is a timing diagram illustrating the circuit operation of FIG. 15.

Fig. 17 is a block diagram showing one embodiment of data output installed in a memory.

Fig. 18 is a block diagram showing the first embodiment of the / CS output section and the data output section provided in the controller.

19 is a block diagram illustrating an embodiment of a data input unit installed in a controller.

Fig. 20 is a block diagram showing an embodiment of a data input / output circuit provided in a memory.

21 is a circuit diagram of an example of a configuration of a register and a receiving gate shown in FIG. 20;

Fig. 22 is a block diagram showing the second embodiment of the / CS output section and the data output section provided in the controller.

FIG. 23 is a circuit diagram of a configuration example of a register and a receiving gate shown in FIG. 22; FIG.

24 is a block diagram illustrating a second principle of the present invention.

Fig. 25 is a block diagram showing an embodiment of a data input / output unit of a memory corresponding to the second principle of the present invention.

Fig. 26 is a block diagram showing another embodiment of a data input / output unit of a memory corresponding to the second principle of the present invention.

Fig. 27 is a block diagram showing one embodiment of a data input / output unit of a memory corresponding to both the first and second principles of the present invention.

<Explanation of symbols for main parts of the drawings>                 

10: controller

11 interface section

12: register

13: memory

14: interface unit

15: register

16: data bus

17a to 17d: register

18: interface unit

19a to 19d: interface unit

20a to 20d: memory core

The present invention relates to a semiconductor device, and more particularly, to an interface of a semiconductor device.

In general, in the case of sending data from the semiconductor device A to the semiconductor device B, for example, the following 16-bit wide data D1 and D2 are considered to be sent in sequence.

D1 ： 1100110011001100                         

D2: 1100110011001101

In this example, the difference is the last 1 digit and the rest is the same data. Consecutive moving image data and the like are generally almost the same in comparison with the data before and after, and often different in part. Therefore, it can be said that it is very wasteful data as it is. To solve this problem, data is compressed to be written or transmitted to a recording medium.

By the way, it is sometimes necessary to transfer raw data between semiconductor devices as they are without compressing them. For example, when processing image data, it is necessary to exchange data between uncompressed data and uncompressed data between semiconductor devices.

However, in order to transmit the original data as it is, a large amount of unnecessary information is included in the amount of information to be transmitted and consumes unnecessary power.

Accordingly, an object of the present invention is to solve the problems of the prior art and to provide a semiconductor device which can efficiently transmit data and has little useless power consumption.

The present invention includes a register for holding first information and an information generation circuit for receiving the first signal from the outside and generating second information, wherein the first signal is a signal indicating inversion of the first information, The information generation circuit includes a semiconductor device that generates the second information based on the first information and the first signal.                         

The first signal is a signal indicating inversion of the first information. Therefore, information before inversion, that is, second information, can be generated from the first information and the first signal. By receiving the first signal indicating the inversion, the second information of the original (before inversion) can be generated. Therefore, the waste of information amount is eliminated compared with the case where nothing is processed, and power consumption can be reduced.

In addition, the present invention includes a register holding first information and an information generating circuit that receives second information and outputs a first signal to the outside, wherein the first signal is held in the register. And a semiconductor device that is a signal based on a logical operation of the information and the second information received by the information generating circuit, the signal representing the inversion of the first information. Similarly, waste of information amount is eliminated and power consumption can be reduced.

The first information may be data last processed by the semiconductor device by rewriting the first information held in the register into the second information as described in claim 3. The first information may be received from the outside (representative data used in the second principle of the present invention described later) as described in claim 4.

The first or second information is data, an address, or the like.

First, the first principle of the present invention will be described with reference to FIG.

1 shows a system in which two semiconductor devices 10 and 13 are connected via a data bus 16. In the example of FIG. 1, the semiconductor device 10 is a controller, and the semiconductor device 13 is a semiconductor memory device (one memory chip, hereinafter referred to simply as a “memory”) controlled by the controller 10. The controller 10 has an interface portion 11 having a register 12. Similarly, the memory 13 also includes an interface unit 14 having a register 14.

The first principle of the present invention is described as an example of the aforementioned data transmission. When D1: 1100110011001100 and D2: 1100110011001101 are transferred from the controller 10 to the memory 13, in the prior art, D1 and D2 were sent as they are. On the other hand, in the first principle of the present invention, D1 is sent first, and then only bits that are different (inverted) from the bits of D1 in the data D2. In other words, instead of transmitting the data D2, D2 ': 0000000000000001 is transmitted. Receiving this, the memory 13 reproduces the data D2 from the immediately preceding data D1 and the transferred data D2 '. The same applies to the case of transferring data from the memory 13 to the controller 10.

That is, the controller 10 and the memory 13 respectively hold the last data exchanged in the registers 12 and 15, and transmit only the higher bits of the next data and the data stored to the counterpart. Then, the receiving side reproduces the data transmitted this time from the received data and the stored data. The inverted bits are transmitted in pulses. Hereinafter, such a pulse may be called a data inversion pulse signal.

This process will be described in detail with reference to the sequence shown in the lower part of FIG. This sequential order shows the case where the controller 10 writes data to the memory 13.

Step 1: First, the controller 10 issues a refresh command for instructing a refresh. This refresh command resets the register 12 of the controller 10 and the register 15 of the memory 13 to 0000. The reset value is not limited to 0000, and may be any value as long as the registers 12 and 15 are reset to the same value.

Step 2: The controller 10 writes data 1011 into the memory 13. The controller 10 takes an exclusive logical sum (Exclusive-OR: EX-OR) between the data 1011 and the data 0000 in the register 12 and transmits the result to the memory 13 via the data bus 16. The memory 13 receives the data 1011 and inverts the contents of the register 15 with respect to the position of "1" to reproduce the data 1011. In this example, since 0000 is stored in the registers 12 and 15, the transmitted data and the reproduced data are equal to 1011. Then, the controller 10 and the memory 13 rewrite the contents of the registers 12 and 15 to 1011, respectively. The reproduced data 1011 is also transmitted to and stored in a memory core inside the memory 13.

Step 3: The controller 10 writes data 1010 to the memory 13. The controller 10 takes an exclusive logical sum of the data 1010 and the data 1011 of the register 12 and, as a result, transfers 0001 to the memory 13. The memory 13 receives data 0001, inverts the contents of the register 15 with respect to the position where " 1 " is located, and reproduces the data 1010. The controller 10 and the memory 13 rewrite the contents of the registers 12 and 15 to 1010, respectively.                     

The same processes as steps (4) and (5) are repeated below.

In this manner, the last data exchanged in both the controller 10 and the memory 13 is held in the registers 12 and 15, and only the bits which are higher (inverted) between the data to be transferred and the data retained are transmitted. Since the reception side reproduces the data transmitted from this data and the data held therein, the number of times of sending data "1" is greatly reduced, and power consumption at the transmission side and the reception side can be reduced. For example, instead of transmitting the data 1010, in step 3, data 0001 is transmitted, thereby reducing the power consumption of one bit. In particular, the effect of the case where the data before and after the same as the moving picture data is almost the same but only partly different is absolute.

FIG. 1 shows a sequential order when the controller 10 writes data to the memory 13, but the same applies to the case where the data is read from the memory 13 and transmitted to the controller 10.

In summary, the controller 10 and the memory 13 include the registers 12 and 15 which hold the first information (the first data after the refresh or the last data exchanged) and the first signal (exclusive logical agreement) from the outside. An information generating circuit (internal circuit of the controller 10 or the memory 13) that receives the signal transmitted on the bus 16 as a result of the operation and generates the second information, for example, the interface unit 10, 13; A circuit provided in the circuit, wherein the first signal is a signal indicating an inversion of the first information (output of an exclusive OR operation), and the information generating circuit is based on the first information and the first signal. It can be said that the semiconductor device generates the second information (for example, by performing an exclusive OR operation).

In addition, the present invention includes an information processing method, comprising the steps of holding first information (first data after refresh or last data exchanged) in registers 12 and 15, and a first signal received from outside [ A signal to be transmitted on the bus 16 as a result of the operation of the exclusive OR; and generating the second information based on the first information and transmitting the second information to a predetermined circuit. An information processing method which is a signal indicating inversion.

In addition, the controller 10 and the memory 13 store the registers 12 and 15 and the second information (for example, the controller 10) that hold the first information (the first data after the refresh or the last data exchanged). ) Is an information generating circuit (controller 10 or an internal circuit of the memory 13) that receives the write data of the &quot;) and outputs the first signal to the outside (the memory 13 in the example of FIG. 1). For example, a circuit provided in the interface units 10 and 13, wherein the first signal is a logical operation (eg, the first information held in the register and the second information received by the information generating circuit). For example, the semiconductor device is a signal based on an exclusive-OR operation.

In addition, the present invention includes an information processing method, comprising the steps of holding first information (first data after refresh or last data exchanged) in the registers 12 and 15, received second information and the above-mentioned second information. A step of generating a first signal and transmitting it to the outside by performing a logical operation (for example, an exclusive OR operation) of one information, wherein the first signal is a signal indicating an inversion of the first information.                     

In addition, in the above description, the refresh instruction is used to reset the registers 12 and 15. However, since the refresh is periodically required when the memory 13 is a DRAM, the controller 10 periodically refreshes the DRAM. Issue a command. Therefore, if the registers 12 and 15 are periodically reset using this, even if the contents of the registers 12 and 15 are different from each other, the resets are reset at each refresh, thereby minimizing the occurrence of errors. have.

The registers 12 and 15 may be signals other than the refresh instruction. For example, a power on reset signal generated internally when power is applied to a semiconductor device such as the controller 10 or the memory 13 may be used to control stand-by. The reset may be performed using a signal (for example, a clock enable signal CKE of a synchronous DRAM).

As described later, the first principle of the present invention can be applied not only to data transmission but also to address signal transmission.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment and Example of this invention are described. In the following description, the phrases &quot; read data &quot; and &quot; write data &quot; are used because the data transfer between the controller and the memory is taken as an example. In the memory as well as the controller, such phrases are used in the following meanings.

Data to be sent from the controller to the memory: write data

Data to be sent from the memory to the controller: read data

Thus, for example, write data is data to be received in a memory and data to be transmitted to a controller.

<1st embodiment of this invention>

2 is a block diagram showing an embodiment of the present invention. The system shown is a configuration in which the controller 10 controls four memories 13a, 13b, 13c, and 13d. For the address, write data and read data transferred between the controller 10 and the four memories 13a to 13d, the first principle of the present invention mentioned above is applied.

The controller 10 and the four memories 13a to 13d are mutually connected via the data bus 16D, the address bus 16A, the command bus 16C, the clock line 21 and the chip select signal line 22. Connected. The data bus 16D is terminated at the predetermined voltage VR via the resistor 24, and the clock signal line 21 is similarly terminated at the predetermined voltage VR via the resistor 23. The predetermined voltage VR corresponds to logic "0" (high level H). The address bus 16A and the data bus 16D transmit a low level data inversion pulse signal when transmitting data "1". Immediately after refreshing, the original transmission data is output to the data bus 16D.

The controller 10 has registers 17a to 17d and an interface unit 18 corresponding to the memories 13a to 13d, respectively. Each register 17a to 17d corresponds to the register 12 in FIG. The memories 13a to 13d include memory cores 20a to 20d and interface units 19a to 19d, respectively. The registers in each of the interface sections 19a to 19d correspond to the registers 15 in FIG. The interface unit 18 of the controller 10 and the interface units 19a to 19d of the memories 13a to 13d respectively include a data bus 16D, an address bus 16A, a command bus 16C, and a clock line 21. And the chip select signal line 22.

The registers 17a to 17d of the controller 10 each have an address register RegADD_C, a write data register RegDW_C and a read data register RegDR_C. The register for address (RegADD_C) holds the reset address value or the last exchanged address value. The write data register (RegDW_C) holds the reset write data value or the last write data value sent and received. The register for read data (RegDR_C) holds a reset read data value or a last read / received data value. The interface 18 is an interface that can be selectively connected to a plurality of semiconductor devices (memory 13a to 13d in FIG. 2). The interface 18 should be transmitted by taking an exclusive logical sum between the register value described with reference to FIG. 1 and the data to be transmitted this time. And a structure that calculates and outputs the data or address to the corresponding bus, and reproduces the received data by taking an exclusive logical sum of the register value and the data received from the corresponding bus. In addition, the detail of such a structure is mentioned later.

The interface units 19a to 19d of the memories 13a to 13d each have an address register RegADD, a write data register RegDW and a read data register RegDR. The address register RegADD of the interface units 19a to 19d corresponds to the address register RegADDC of the registers 17a to 17d of the controller 10, respectively, and stores the reset address value or the last address exchanged. Keep it. The write data registers RegDW of the interface units 19a to 19d correspond to the write data registers RegDWC of the registers 17a to 17d of the controller 10, respectively, and reset or receive the reset write data value or the last time. Holds the write data value. The read data register RegDR of the interface units 19a to 19d corresponds to the read data register RegDRC of the registers 17a to 17d of the controller 10, respectively, and is a reset read data value or a last read or received read. Hold the data value. The interfaces 19a to 19d are obtained from an exclusive logical sum of the register value described with reference to FIG. 1 and the data to be transmitted this time, from the configuration corresponding to the data or address to be transmitted and the address to be calculated and output to the corresponding bus. And an exclusive logical OR with the received data to reproduce the received data. In addition, the detail of such a structure is mentioned later. The memory cores 20a to 20d include an array in which a plurality of memory cells are arranged in a matrix.

Next, operation | movement of the structure shown in FIG. 2 is demonstrated.

Initially, the controller 10 issues a refresh instruction to the memories 13a to 13d, registers (RegADDC, RegDWC, RegDRC) of the registers 17a to 17d of the controller 10, and the interface section (13a to 13d). The registers (RegADD, RegDW, RegDR) in 19a to 19d are reset (process corresponding to step 1 in Fig. 1). For example, each register resets each bit to "0".

Next, the controller 10 turns on any of the chip select signals CSa to CSd corresponding to the memory to be selected and issues a command. For example, when the chip select signal CSa is turned on, the register 17a of the controller 10 is turned on and the memory 13a is selected through the signal line 22. If the command is a write command, the interface unit 18 of the controller 10 takes an exclusive OR between the address and data to be transmitted and the data in the registers (RegADDC, RegDWC, RegDRC), and writes the result of the operation into these registers. At the same time, the data is transmitted to the address bus 16A and the data bus 16D (process corresponding to step 2 in FIG. 1). The selected memory 13a receives an exclusive OR output from the address bus 16A and the data bus 16D, respectively, and takes an exclusive OR between the received data and the data of the registers RegADD, RegDW, RegDR. The operation results are written to these registers and output to the memory core 20a (process corresponding to step ② in Fig. 1). Hereinafter, the same process is repeated.

On the other hand, when the instruction is a read instruction, the interface unit 19a of the memory 13a takes an exclusive logical OR between the address and data to be transmitted and the data in the registers RegADD, RegDW, RegDR, and respectively calculates the result of the operation. The data is written to these registers and transmitted to the address bus 16A and the data bus 16D. The controller 10 receives an exclusive OR output from the address bus 16A and the data bus 16D, respectively, and takes an exclusive OR of the received data and the data of the registers RegADDC, RegDWC, and RegDRC, and outputs the result of the operation. It writes to these registers and outputs them to the internal circuit.

In this way, the exclusive OR output with " 1 " only in bit positions different from the immediately preceding data is output to the address bus 16A and the data bus 16D. Therefore, the number of times that the address bus 16A or the data bus 16D transmits a low level pulse is reduced by the logic " 1 ", so that power consumption can be reduced.

First embodiment of the memory-side data input unit

Next, a first embodiment of the data input unit provided inside the interface units 19a to 19d of each of the memories 13a to 13d will be described. The first embodiment is a data input unit in which data from the outside is put in synchronization with a clock.

Each interface unit 19a to 19d includes a data input unit for inputting data (write data) from the data bus 16D. 3 shows a first embodiment of this data input unit. The data input section has a clock generating section 25, a command input circuit / command decoder 26, an OR gate 27, and n data input circuits 28 _{1 to} 28 _n . The clock generator 25 receives the clock signal from the clock line 21, generates an internal clock CLK1, and outputs the internal clock CLK1 to the command input circuit / command decoder 26 and the data input circuits 28 _{1 to} 28 _n . . The command input circuit / command decoder 26 receives the corresponding chip select signal / CS (any of CSa to CSd) and turns it ON (enabled), inserts a command supplied from the command bus 16C, and decodes it. . According to the result of decoding, either of the three control lines 33a to 33c is driven. The command input circuit / command decoder 26 drives the control line 33a to output an internal read command when the command is a read command, and outputs an internal write command by driving the control line 33b when the command is a write command. In the case of a refresh command, the control line 33c is driven to output an internal refresh command.

Each of the data input circuit (28 ₁ ~28 _n) has a comparator 29, a synchronous latch 30, a pulse to biological father 31 and the register (RegDW). A data input circuit (28 ₁ ~28 _n) is the exclusive-or operation mentioned earlier. The register RegDW has a flip flop (F / F) 32. The data input circuits 28 _{1 to} 28 _n are connected to respective bus lines of the data bus 16D, respectively. For example, when the data bus 16D is 16 bits wide, 16 data input circuits 28 _{1 to} 28 ₁₆ are provided. The comparator 29 compares the corresponding one bit of input data (here, N) with the threshold Vref and determines the logic value of the input data IN. The synchronous latch 30 receives the internal clock CLK1 and latches the output of the comparator 29. The pulse generator 31 receives the output signal N1 of the synchronous latch 30 when the control line 33b is ON, that is, when a write command is received, and generates a predetermined pulse N2. Pulse N2 is given to the clock terminal of flip flop 32. The / Q output of the flip flop 32 is connected to the D terminal, and the Q output is an output signal of the data input circuit 28 ₁ . Flip flop 32 is reset to the output of OR gate 27. The OR gate 27 receives a reset signal (generated when the chip select signal / CS turns off) or a refresh command outputted by the command input circuit / command decoder 26 (when the control line 33c turns on). It is reset. When reset, the Q output becomes "0".

4 is a timing diagram illustrating the operation of the circuit shown in FIG. 3. 4 is an operation when write data IN is supplied to the data input circuit 28 ₁ of FIG. First, a command is sent in synchronization with the clock CLK. In the example of FIG. 4, the refresh instruction is supplied first, and the flip flop 32 is reset. Subsequently, the write data IN and the write command are supplied (part of 1 in FIG. 4). The write data IN passes through the comparator 29 and is latched by the synchronous latch 30. The synchronous latch 30 synchronizes with the falling of the clock CLK (actually the internal clock CLK1 generated now), and latches the data IN. The latched output becomes N1 and is sent to the pulse generator 31. N1 is not shown in the timing diagram of FIG.

The command input circuit / command decoder 26 decodes this write command to drive the control line 33b. As a result, the pulse generator 31 is in the enabled state, and generates pulse N2 in response to the data IN1 as indicated by? In FIG. In other words, the write data " 1 " is synchronized with the clock and latched to generate one predetermined pulse. Pulse N2 inverts the state of flip flop 32 and the Q output changes from low level to high level. That is, the data "1" first transmitted after the refresh is output to an internal circuit (for example, the memory core 20a shown in FIG. 2) not shown as OUT and stored in the flip flop 32.

Next, at the timing (2), a write command and data IN of "0" (transmitted by high level pulses) are transmitted. When data IN is "0", it means that the exclusive OR operation result of the transmission side is "0", that is, this write data is the same as the previous write data. The synchronous latch 30 latches the high level and outputs N1 to the pulse generator 31. The pulse generator 31 does not respond to the high level signal N1 and does not generate the pulse N2. Thus, the state of the flip flop 32 is not reversed, and its output OUT does not change while being at a high level.                     

Next, at the timing (3), a write command and data of "1" (transmitted by a low level pulse) are transmitted. In other words, the data transmitted in ③ is the inversion data of the data transmitted in ②. In this case, the same operation as the timing 1 is performed, and the flip-flop 32 receives the pulse N2 and the state is reversed. Thus, the output OUT drops from the high level to the low level.

Hereinafter, the same operation is performed at the timings ④ and ⑤. The data transmitted from 1 to 5 is 10110. In other words, the original transmission data is 11011. The output OUT of the data input circuit 28 ₁ is 11011, and original transmission data (write data) is correctly reproduced. The power consumption for one bit is reduced by transmitting the exclusive logical sum output 10110 instead of transmitting the original data 11011 as it is.

Each timing ①~⑤, n parallel data bits have been transferred to the data bus (16D), a data input circuit (28 ~28 _{2 n)} other than the above-described data input circuit (28 ₁₎ is also the above-mentioned data input circuits It works like (28 ₁ ).

<Example of Memory Side Address Input Unit>

5 illustrates an embodiment of an address input unit provided inside the interface units 19a to 19d of each of the memories 13a to 13d.

Each interface unit 19a to 19d includes an address input unit for inputting an address from the address bus 16A. The address input unit is substantially the same as the first embodiment of the data input unit shown in FIG. That is, the address input unit, like the data input unit, has a clock generator 35, a command input circuit / command decoder 36, an OR gate 37, and m (m is an arbitrary integer, Equivalent)), and an address input circuit 38 _{1 to} 38 _m . Each address input circuit (38 ₁ ~38 _n) has a comparator 39, a synchronous latch 40, a pulse generating unit 41 and the register (RegADD) which receives the address N. The register RegADD has a flip flop 42.

The difference between the address input section and the data input section is that the pulse generating section 41 is controlled by both the control line 43a for turning on in response to a read command and the control line 43b for turning on in response to a write command. This is because the address input circuits 38 _{1 to} 38 _n are operated in both the read command and the write command.

In FIG. 5, the operation of the address input unit is the same as the operation shown in the timing diagram shown in FIG. 4, and a description thereof will be omitted.

Second Embodiment of the Memory-Side Data Input Unit

Next, a second embodiment of the data input unit provided inside the interface units 19a to 19d of each of the memories 13a to 13d will be described.

6 is a block diagram showing a configuration of a data input unit according to a second embodiment of the present invention. The same reference numerals are assigned to the same components as those shown in FIG. 3 among the components shown in FIG. 6. The second embodiment is a data input unit in the form of detecting the low edge (edge falling from high to low) of the data IN.

Also in place of the data input circuit (28 ₁ ~28 _n) shown in Fig. 3 are used, the data input circuit (128 ₁ ~128 _n). 6, only the data input circuit 128 ₁ is shown. In addition, a 1/2 divider 44 is provided for dividing the internal clock CLK1 at the division ratio 2 to generate the internal clocks CLK2 and / CLK2 in a complementary relationship.

The data input circuit 128 ₁ has a write register RegDW having a comparator 29, an inverter 46, an input latch portion 45, a pulse generator 31, and a flip flop 32. The input latch unit 45 has two lines of detection units that operate alternately by detecting the low edge of the data IN. One of the detection sections of the two systems (hereinafter referred to as "first low edge detector") is a circuit related to the internal clock CLK2, and includes a gate 47, a comparator 48, a latch 49, and a delay circuit ( 50). The other detection part (hereinafter referred to as "second low edge detection part") is a circuit related to the internal clock / CLK2, and has a gate 51, a comparator 52, a latch 53, and a delay circuit 54. . In addition, in order to make it easy to understand which system belongs to, the number of 1 or 2 is attached after each part name. The input latch section 45 also includes an OR gate 55, a delay circuit 56, and a synchronous latch 30.

FIG. 7 is a timing diagram illustrating the operation of the data input unit shown in FIG. 6. As shown in the relationship between the clock CLK and the data IN shown in FIG. It is accepted by the command Write2. The pulse 3 is generated beyond the timing t4 of the clock CLK, but the L edge of the pulse 3 is generated between the timings t3 and t4, and therefore is received by the write command Write3. The second half of the pulse ③ appears between the timings t4 and t5 of the clock CLK, but this part is ignored and the pulse 4 is accepted as the write command Write4. Since no L edge has occurred in the data IN between the timings t5 and t6 of the clock CLK, the write command Write5 does not receive a pulse. In addition, in Fig. 7, the pulse? Is ignored if the write command Write2 is not input.

The first low edge detector of the input latch unit 45 mentioned above detects the L edge of the data IN which the internal clock CLK2 occurs in the period of the low L, and the second low edge detector detects the internal clock / CLK2 of the low. The L edge of data IN occurring in the period is detected. By alternately operating the first and second row edge detectors, detection of the L edge of the data IN in all periods is possible.

The data IN is inputted as / IN through the inverter 46 because the input of the H (high) pulse is easier to understand the operation of FIG. 7 than the L pulse.

The operation of the first row edge detector will be described. The latch 49 is reset while the internal clock CLK2 is at the H level, and its output N3 is L. When the internal clock CLK2 reaches the L level, the reset is released in the latch 49, and the latch 49 is in a state of waiting for the output N2 of the comparator 48 to go to the H level. Although the function of the gate 47 is mentioned later, it is a connection state at this time. When the L pulse is input to the data IN, a high pulse occurs at the node N1. The comparator 48 determines whether the H edge (edge rising from low to high) of the internal clock CLK2 and the H edge of the node N1 are faster. If the H edge of node N1 is fast, then output N2 goes to H, which is latched to latch 49. The H level signal is transmitted to the nodes N3 and N7, latched in the synchronous latch 30 in synchronization with the internal clock CLK1, and output to the pulse generator 31 as an output signal N8. If the write command corresponding to the data IN is input, the control line 33b is turned on (also can be said that an internal write command is generated), and the pulse generator 31 generates a pulse N9 to flip the flop. Reverse the state of (32). In the case of Fig. 7, the output OUT is inverted from "0" to "1" (inverting?).

Here, the reason why the latch 49 is necessary is that, when the internal clock CLK2 ends the pulse generation during the L level as shown by IN 1 in FIG. 7, the determination result of the comparator 48 also disappears with the end of the IN pulse. This is because it is necessary to hold them in the latch 49.

In addition, the function of the gate 47 is to disregard the later portions of the pulse which are input beyond the H edge of the clock CLK as shown by IN 3 in FIG. When the comparator 48 has H of the node N1 faster than the internal clock CLK2, the node N2 becomes H, and this state is maintained as long as the node N1 is H. While node N2 is at the H level, gate 2 is cut, and data IN is not transferred to the circuit of the second row edge detector. Thereafter, when the node N1 becomes L level, the node N2 becomes L level, the gate 51 is in a connected state, and when a pulse is input while the internal clock / CLK2 is L level, the second low edge detection circuit generates data. Insert IN.

In addition, in the structure shown in FIG. 6, use of an input pulse whose pulse width (length of an L level part) of input data is likely to exceed one clock length is prohibited in principle. In addition, the latch 49 is reset to the output of the delay circuit 50 which delays the internal clock CLK2 only a predetermined time. Similarly, the latch 53 is reset to the output of the delay circuit 54 which delays the internal clock / CLK2 only a predetermined time. In addition, the synchronous latch 30 is reset to the delay circuit 56 which delays the internal clock CLK1 only for a predetermined time.

FIG. 8 is a diagram illustrating an example of a circuit configuration of the input latch unit 45 of the data input unit shown in FIG. 6. Gate 47 is composed of a NOR gate 47a. The NOR gate 47a performs an NOR operation on the output of the comparator 29 and the output of the inverter 58. Comparator 48 consists of NAND gates 48a and 48b. The latch 49 consists of NAND gates 49a and 49b. The delay circuit 50 is composed of an inverter 50a and a delay element 50b. Similarly, the gate 51 consists of a NOR gate 51a. The NOR gate 51a performs an NOR operation on the output of the comparator 29 and the output of the inverter 57. The comparator 52 consists of NAND gates 52a and 52b. The latch 53 is composed of NAND gates 53a and 53b. The delay circuit 54 consists of an inverter 54a and a delay element 54b. The OR gate 55 is composed of a NOR gate 55a and an inverter 55b.

The circuit operation of FIG. 8 is as shown in FIG.

Third Embodiment of the Memory-Side Data Input Unit

Next, with reference to FIG. 9, the 3rd Example of the data input part provided in the interface part 19a-19d of each memory 13a-13d is demonstrated. The third embodiment is a data input unit in which the level of the data IN is inserted in the rise of the chip select signal / CS. In Fig. 9, the same reference numerals are given to the same components as those shown in Fig. 3.

The command input circuit / command decoder 26 detects the fall of the chip select signal / CS, outputs the internal chip select signal CS1, and outputs it to the latch 30. The latch 30 inserts data IN in synchronization with the internal chip select signal CS1. The other circuit configuration is the same as the circuit configuration shown in FIG. 3.

10 is a timing diagram illustrating an operation of a data input unit shown in FIG. 9. After the refresh, the latch circuit 30 latches the low pulse of the data IN in response to the fall of the chip select signal / CS. The pulse generator 31 is in an enabled state when the control line 33b is turned on, receives the pulse N1 from the latch 30, and outputs the pulse N2 to the flip flop 32. The flip-flop 32 receives the pulse N2, in other words, the state is reversed by the rise of the node N2. By the inversion of this state, the output OUT of the flip flop 32 changes from L to H level.
Likewise below, the state of the flip-flop 32 is inverted when the data IN is at the low level when the chip select signal / CS falls.

delete

<Fourth embodiment of the memory-side data input unit>

Next, with reference to FIG. 11, the 4th Example of the data input part provided in the interface part 19a-19d of each memory 13a-13d is demonstrated. The fourth embodiment is a data input section in which the L edge of the data IN is detected asynchronously (clock CLK or chip select signal / CS is not synchronized). In Fig. 11, the same reference numerals are given to the same components as those shown in Fig. 6.                     

In the circuit configuration of FIG. 11, the input latch unit 60 is provided in place of the input latch unit 45 shown in FIG. 6, and the half divider 44 shown in FIG. 6 is not provided. It differs from the circuit structure shown in FIG. The input latch unit 60 includes a comparator 48, a latch 49, and a delay circuit 50. The input latch section 60 is connected to the L edge of the input data IN and the inverted data / IN directly output from the inverter 46 while the chip select signal / CS (i.e., CS1) is in the ON state (input accepting period). When the H edge is detected, the output signal N3 is output to the pulse generator 31.

12 is a timing diagram illustrating an operation of the circuit of FIG. 11. The first data IN after refresh is the L pulse (1). Since the internal chip select signal CS1 changes the inversion data / IN from L to H level within the input acceptance period, the comparator 48 outputs the pulse N2 to the latch 49. The latch 49 holds the H pulse and outputs the H level signal N3 to the pulse generator 31. The pulse generator 31 is in an enabled state (in other words, by an internal write command) in response to the write command Write1 being turned on (in other words, by an internal write command), and flips the pulse N4 in response to the H level signal N3. Output to flop 32. The flip-flop 32 receives this and the state is reversed, and the output OUT changes from L to H level.

At the timing of the next L pulse (2) of the data IN, the internal chip select signal CS1 is in the OFF state, and the comparator 48 does not detect this L pulse. In Fig. 12, the pulse shown by the dotted line on the time axis indicating the signal (node) N2 is not detected by the comparator 48, which shows that it is not latched by the input latch unit 60 as a result.                     

The reset of the latch 49 is performed with the output signal of the delay circuit 50 which delays the internal chip select signal CS1 only for a predetermined time. In the example shown in figure, the delay time corresponds to half a period of the internal chip select signal CS1.

Next of the data IN, the L pulse ③ is processed similarly to the L pulse of ① mentioned above. As a result, the state of the flip-flop 32 changes in response to the L pulses of 1 and 3 of the input data, that is, the write data, and the output OUT changes from L to H to L, respectively.

<Fifth Embodiment of the Memory-Side Data Input Unit>

Next, a fifth embodiment of the data input unit provided in the interface units 19a to 19d of each of the memories 13a to 13d will be described with reference to FIG. The fifth embodiment is a data input section in which the L edge of the data IN is asynchronously detected, which is an improved version of the above-described fourth embodiment. In Fig. 13, the same reference numerals are given to the same components as those shown in Fig. 6.

Although the circuit configuration of the fifth embodiment is similar to the circuit configuration of the second embodiment shown in FIG. 6, the input latch portion 62 shown in FIG. 13 includes one low edge detector. The low edge detector includes a gate 47, a comparator 48, a latch 49, and a delay circuit 50. The circuit composed of the gate 51, the comparator 52 and the inverter 63 controls the ON / OFF of the gate 47.

FIG. 14 is a timing diagram showing the operation of the fifth embodiment shown in FIG. The L pulse? Of data IN is converted into the data / IN of the H pulse in the inverter 46, passes through the gate 47, and is given to the comparator 38 as N1. At this time, since the comparator 38 receives the internal chip select signal CS1 of the L level, the comparator 38 outputs the output N2 of the H pulse to the latch 49 and the gate 51. The latch 49 latches this H pulse and supplies the output N3 of the H level to the pulse generator 31. The pulse generator 31 responds to the internal command Write obtained by decoding the write command Write1, and gives the flip-flop 32 the pulse output N4. As a result, the output OUT changes from L to H level.

On the other hand, the gate 51 is in the connected state by receiving the signal N2 of the H pulse, and the inversion data / IN passes through the gate 51 and is given to the comparator 52. At this time, since the inversion internal chip select signal / CS1 is at the H level, the comparator 52 cannot detect the rise of the inversion data / IN, and its output N6 is at the L level. The gate 47 is in the connected state at the output N6 of the L level.

When the next L pulse? Of the input data IN is received, since the internal chip select signal CS1 is H, the comparator 48 is in a disabled state, and the comparator 52 is in an enable state. Since the node N2 is at the L level, the gate 51 is in the connected state. Therefore, the comparator 52 detects the rise of the inversion data / IN, and sets the output N6 to H level. Upon receiving it, the gate 47 is turned off and its output N1 is at the L level. Therefore, the output N2 of the comparator 48 is also L. At this time, the latch 49 continues to hold the H level. In other words, the input latch portion 62 does not detect the L pulse (2) (not latch). This is because the L pulse? Has already fallen at the time when the chip select signal / CS falls, and the L pulse at this timing is ignored.

The latch 49 is reset to the output of the delay circuit 50 which delays the internal chip select signal CS1 only for a predetermined time and is reset to the L level. That is, the latch is released.

The L pulse 3 of the next data input IN is processed in the same manner as 1 described above, and inverts the flip flop 32.

As described above, the output OUT changes only two times from L to H to L according to the three L pulses 1, 2, and 3 of the data IN.

In the third to fifth embodiments, the chip select signal / CS is used to insert the data IN, but other command signals may be used.

<Sixth Embodiment of Memory-Side Data Input Unit>

Next, with reference to FIG. 15, the 6th Example of the data input part provided in the interface part 19a-19d of each memory 13a-13d is demonstrated. The sixth embodiment is a data input unit which adds an improvement from the viewpoint of power consumption to the first embodiment shown in FIG. In Fig. 15, the same reference numerals are given to the same components as those shown in Fig. 3.

The circuit configuration shown in FIG. 15 has a configuration in which the first input stage composed of the comparator 29 is controlled by the internal chip select signal CS1 output from the command input circuit / command decoder 26. This differs from the circuit configuration shown in FIG. Comparator 29 is only enabled (activated) when internal chip select signal CS1 is ON. That is, when it is OFF, the comparator 29 is in a disabled state. As a result, when the chip on which the data input unit is mounted is not selected, the comparator 29 does not consume unnecessary power.

16 is a timing diagram illustrating an operation of the circuit configuration shown in FIG. 15. By inputting the chip select signal / CS before the rising edge of the clock CLK for a predetermined period (1/2 cycles in the example of FIG. 16), the L level of the data IN is inserted after the comparator 29 is enabled. Doing.

The thinking method of the sixth embodiment, in which the input first stage is only enabled when necessary, is similarly applicable to the first to fifth embodiments.

<Example of Memory-side Data Output Unit>

Next, with reference to FIG. 17, one Example of the data output part provided in the interface part 19a-19d of each memory 13a-13d is demonstrated. The data output section described below is applicable to both synchronous and asynchronous.

Figure 17 outputs data representing the portion has an OR gate 65, a acquisition gate 60, a register 67 and the n data output circuit (68 ₁ ~68 _n). Each of the data output circuits (68 ₁ ~68 _n) is provided with an exclusive OR gate 69, the flip-flop 70, a delay circuit (71), AND gate 72 and transistor 73. Read data from the memory core (shown in FIG. 2) is given to the receiving gate 60 and is given to corresponding data output circuits 68 _{1 to} 68 _{n in} units of bits. The reception gate 60 enters the connected state in response to a data output pulse from the memory core, and outputs read data to the register 67. The refresh command or reset signal generated internally from the controller 10 or in memory through the command bus 16C (FIG. 2) is passed through the OR gate 65 to the register 67. Upon receiving this signal, the register 67 is reset. The register 67 is reset every time data is read.

The exclusive OR gate 69 of the data output circuit 68 ₁ performs an exclusive OR operation on the corresponding bit of read data and the corresponding bit of read data read from the register 67. Read data read from the register 67 is read data immediately before the data read from the memory core. Therefore, the exclusive OR gate 69 detects whether or not the current data is inverted with respect to the previous data. When inverted, the exclusive OR gate 69 outputs the H level output N1 to the flip flop 70. The flip flop 70 latches the H level output N1 in response to the data output pulse and outputs H to the Q output. The data output pulse is delayed slightly in delay circuit 71 and is given to AND gate 72. The AND gate 72 outputs a pulse having a width corresponding to the timing difference between the Q output and the output from the delay circuit 71. The transistor 73 is composed of a field effect transistor such as an N-channel MOS transistor, and the corresponding bus line of the data bus 16D is ground level (low level) in response to an H pulse output from the AND gate 72. Set to. The drain of the transistor 73 is connected to a data bus line terminated by a resistor, which is a form of so-called open drain.

<Example of the / CS output section and the data output section of the controller>

Next, an embodiment of a chip select signal output unit (hereinafter referred to as "/ CS output unit") and a data output unit provided inside the controller 10 will be described with reference to FIG.

The / CS output unit inside the controller 10 includes a chip select control circuit 75 and chip select signal output circuits 84a to 84d. The chip select control circuit 75 generates chip select signals for selecting the four memories 13a to 13d shown in Fig. 2 and outputs them to the chip select signal output circuits 84a to 84d. Each chip select signal output circuit 84a to 84d includes an AND gate 85 and a field effect transistor 86 such as an NMOS transistor. The AND gate 85 receives the corresponding chip select signal and the CS output control signal. The CS output control signal is output from a controller (not shown) inside the controller 10, and is a signal that is turned ON when a chip is selected. The output of AND gate 85 controls the gate of transistor 86. The AND gate 86 of the chip select signal output circuits 84a to 84d outputs an active low chip select signal / CSa to / CSd. The chip select signals / CSa to / CSd are respectively supplied to the memories 13a to 13d of FIG. 2 via the command bus 16C.

A data output section OR gate 76, the received control circuit 77, a reset circuit 78, register group 79, multiplexer 83 and data output circuits (87 ₁ ~87 _n) of the controller 10 do. The register group 79 includes four register units 80a to 80d corresponding to the four memories 10a to 10d. Each register unit 80a to 80d includes a receiving gate 81 and a register 82. The register units 80a to 80d correspond to the registers 17a to 17d shown in Fig. 3, respectively. The interface unit 18 of FIG. 3 includes the multiplexer 83 and data output circuits 87 _{1 to} 87 _n of FIG. 18.

The write data is given to the register group 79 and is given to the data output circuits 87 _{1 to} 87 _{n in} units of bits. The reception control circuit 77 receives four chip select signals and, in response to the data output pulses, the unit corresponding to the chip select signal turned on (in the enabled state) from the register units 80a to 80d. The receiving gate 81 is brought into a connected state. As a result, the write data is written to the register 82 of the corresponding unit via the receiving gate that is turned ON. The reset circuit 78 resets the register 82 of the unit selected by the chip select signal in response to a refresh command or a reset signal supplied from the internal circuit of the controller 10 through the OR gate 76.

The write data read out from the registers 82 of the register units 80a to 80d are supplied to the corresponding data output circuits 87 _{1 to} 87 _{n in} units of bits through the multiplexer 83.

The data output circuit (87 ₁ ~87 _n) includes a respective exclusive-OR gate 84, flip-flop 85, a delay circuit 86, the field effect transistor 88, such as an AND gate 87 and the NMOS transistor . This configuration is the same as the data output circuits 68 _{1 to} 68 _n shown in FIG. 17. The exclusive OR gate 84 receives the corresponding bit from the multiplexer 83 and the corresponding bit of the write data, performs their exclusive OR operation, and outputs the operation result to the flip flop 85. The write data received through the multiplexer 83 is write data processed one time ago. Therefore, this exclusive OR operation detects whether or not the current write data is the inversion data of the previous write data. When inverted, the exclusive OR gate 84 outputs an H level output to the flip flop 85. Flip-flop 85 latches the H level output in response to the data output pulse and outputs H to the Q output. The data output pulse is delayed slightly in delay circuit 86 and given to AND gate 87. The AND gate 87 outputs a pulse having a width corresponding to the timing difference between the Q output and the output from the delay circuit 86. The transistor 88 is composed of a field effect transistor such as an N-channel MOS transistor, and sets the corresponding bus line of the data bus 16D to the ground level in response to the H pulse output from the AND gate 87.

<Example of Data Input Unit of Controller>

Next, an embodiment of a data input unit installed inside the controller 10 will be described with reference to FIG. 19.

Controller 10 of the data input unit chip select circuit (75), OR gate 90, the reset circuit (91), n input circuits (91 ₁ ~91 _n), respectively corresponding to the four memory (13a~13d) Register units 93a to 93d and a multiplexer 98 are provided. The data input unit is a circuit which receives read data from the data bus 16D and outputs it to an internal circuit including a memory core.

The input circuits 92 _{1 to} 92 _n receive read data from the data bus 16D and output them to the register units 93a to 93d. Each of the input circuits 92 _{1 to} 92 _n includes a comparator, a latch unit, and a pulse generator, and can be configured in the same manner as in the first to sixth embodiments of the data input unit on the memory side mentioned above.

Each of the register units 93a to 93d includes a receiving gate 94 composed of n AND gates 96 and a data register 95 composed of n flip flops. AND gate 96 is at the same time as receiving the read data of n bits from the input circuit (92 ₁ ~92 _n), receives a chip select signal corresponding. The output of AND gate 96 is supplied to the clock terminal of corresponding flip flop 97. The / Q output of each flip flop 97 is connected to the D input, and the Q output is supplied to the multiplexer 98. The reset circuit 91 responds to the refresh command or reset signal supplied through the OR gate 90, and resets the flip flop 97 of one unit indicated by the chip select signal in the units 93a to 93d. . The multiplexer 98 selects a unit corresponding to the chip select signal that is turned on, and outputs the read data output therefrom to an internal circuit including a memory core.

Upon receiving the input circuit (91 ₁ ~91 _n) the inverted data "1" (L pulse), transmitted by the corresponding inverting the state of the flip-flop (97) to the data register 95 through the acquisition gate 94 Data is reproduced.

<Example of Memory-side Data Input / Output Unit>

Next, a data input / output unit provided inside the interface units 19a to 19d of each memory 13a to 13d will be described as a seventh embodiment with reference to FIG. In the seventh embodiment, the write data register RegDW and the read data register RegDR are used together. In FIG. 20, the same reference numerals are assigned to the same components as those shown in the aforementioned drawings.

The data input / output unit has an OR gate 65, a receiving gate 60, a register 67, and a data input / output unit 100. The data input / output unit 100 has n data input / output units 101 _{1 to} 101 _n . Each of the data input-output unit (101 ₁ ~101 _n) is provided with a data input and a pulse generating circuit 102 and the data output circuit 103. The data input circuit 102 includes a circuit from the first embodiment to the sixth embodiment of the above-described data input circuits up to the pulse generator 31 excluding the write register RegDW. The write register RegDW corresponds to the register 67. The data output circuit 103 is, for example, the data output circuits 68 _{1 to} 68 _n shown in FIG. 17. The register 67 (read register RegDR) shown in FIG. 17 also functions as the write register RegDW in FIG.

Read data from the memory core is supplied to the receiving gate 60 and the data output circuit 103 of the data input / output units 101 _{1 to} 101 _n via the internal read data bus 105. The data output circuit 103 outputs a data inversion pulse signal (e.g., L pulse) whose result of the exclusive OR operation corresponds to "1" to the bus 16D. Write data is input from the data bus 16D to the data input circuit 102 where a pulse signal is given to the register 67 when an L pulse indicating data inversion is detected. The register 67 outputs write data or comparison data to the internal write data bus 104. The comparison data is stored in the register 67 through the receiving gate 60 as the last read data for the read data.

FIG. 21 is a circuit diagram showing an example of the configuration of the receiving gate 60 and the register 67 shown in FIG. 20, showing a circuit configuration of one bit. The receiving gate 60 has an inverter 104 and two AND gates 105 and 106. The read data on the internal read data bus 105 is supplied directly to the AND gate 106, and is inverted at the inverter 104 and supplied to the AND gate 105. In addition, the AND gates 105, 106 receive data output control pulses that function as reception control signals.

The register 67 has an OR gate 107 and a set terminal flip flop 108. The output of AND gate 105 is given to the reset terminal of flip flop 108 via OR gate 107. The reset terminal is also given a refresh command (or a reset signal) via the OR gate 107. The output of the AND gate 106 is connected to the set terminal. The clock terminal is given a data inversion pulse signal from the data input and pulse generation circuit 102. The / Q terminal is connected to the D terminal and the Q terminal constitutes the output of the register 67.

The circuit operation of FIG. 21 will be described. When a refresh command (or reset signal) is given to the flip flop 108, the flip flop 108 is reset and the Q output goes to the L level. At the data output, the data output control pulse changes to H level. When the read data is at the L level, the reset terminal goes to H and the Q output goes to the L level. In the case of inserting write data, the data inversion pulse signal from the data input and pulse generation circuit 102 enters the clock terminal of the flip flop 108, and the Q output is inverted.

In this manner, the write area and the read data share the register, thereby saving the chip area.                     

<Other embodiments of the / CS output section and the data output section of the controller>

Next, another embodiment of the chip select signal output unit (hereinafter referred to as "/ CS output unit") and the data output unit provided inside the controller 10 will be described with reference to FIG. 22 as the second embodiment. In this second embodiment, the write data register RegDW_C and the read data register RegDR_C are also used. In Fig. 22, the same reference numerals are given to the same elements as those shown in Fig. 18.

The register group 110 has four register units 111a to 111d corresponding to the four memories 13a to 13d shown in FIG. Each register unit 111a to 111d has two receiving gates 112 and 113 and a register 114. The reception control circuit 77 sets the reception gate 112 of one of the register units 111a to 111d in a connected state based on the chip select signal. The receiving gate 113 of the register units 111a to 111d is controlled in response to the corresponding chip select signal. Write data on the internal write data bus 122 is written to the register 114 through one receiving gate in either of the register units 111a to 111d. The data inversion pulse signal from the data input / output unit 117 described later is written into the register 114 through one of the receiving gates of the register units 111a to 111d. The multiplexer 115 responds to the chip select signal, selects any one of the register units 111a to 111d, and writes the data output therefrom into the register 116. Data (read data or comparison data) read from the register 116 is read on the internal read data bus 121.

The data input / output unit 117 has the same structure as the data input / output unit 100 shown in FIG. 20. The data input / output unit 117 has n data input / output units 118 _{1 to} 118 _n . The data input / output units 118 _{1 to} 118 _n each include a data input and pulse generation circuit 119 and a data output circuit 120. The data input circuit 119 corresponds to the input circuits 92 _{1 to} 92 _n shown in FIG. 19, except for the write register RegDW in the data input circuits of the first to sixth embodiments mentioned above. The circuit up to the generator 31 is included. The write register RegDW corresponds to the register 114. Further, the data output circuit 120, for the data output circuits (87 ₁ ~87 _n) shown in FIG. 18, for example. The chip select signal output circuit 84 shown in FIG. 22 includes chip select signal output circuits 84a to 84d shown in FIG. 18.

FIG. 23 is a circuit diagram illustrating an example of a circuit configuration of the receiving gates 112 and 113 and the register 114 shown in FIG. 22. The receiving gate 112 has an inverter 131 and two AND gates 132 and 133. The receiving gate 136 has an AND gate 136. The register 114 has an OR gate 134 and a flip flop 135. The receiving gate 112 is the same structure as the receiving gate 60 shown in FIG. In addition, the register 114 is the same structure as the register 67 shown in FIG. In the circuit configuration of FIG. 21, the data inversion pulse signal is directly supplied to the clock terminal of the flip-flop 108. In the circuit configuration of FIG. 23, the flip-flop is provided through the receiving gate 113 formed of the AND gate 136. It is supplied to the clock terminal of 135. The AND gate 136 performs an AND operation on the chip select signal corresponding to the data inversion pulse signal. When the chip select signal is ON, a data inversion pulse signal output by the data input and pulse generation circuit 119 is provided to the clock terminal of the flip flop 135 through the AND gate 136. The Q output is once held in the register 116 via the multiplexer 115 and then supplied to the memory core as read data.

Second Principle of the Invention

Next, a second principle of the present invention will be described with reference to FIG.

In the first principle of the present invention described with reference to FIG. 1, the register 12 of the controller 10 and the register 15 of the memory 13 always hold the last exchanged data. In contrast, in the second principle of the present invention, the register 12 of the controller 10 and the register 15 of the memory 13 hold the same representative data. Then, a bit different from the representative data is transmitted as the data inversion signal. This transmission is performed using a pulse, for example.

For example, when a group of data is transmitted, the representative data is transmitted first, followed by a bit different from the representative data. In this case, two types of instructions (WRITE (A)) for transmitting representative data and instructions (WRITE (B)) for transmitting inverted bits are used for the write command. Similarly, the read command includes a command [READ (A)] for outputting read data as it is and a command [READ (B)] for outputting only the bit inverted. The signal is transmitted and received, but when the representative data is transmitted, it is determined as "0" when the L pulse is entered and "1" when it is not entered.

In the example of FIG. 24, the controller 10 writes the representative data 1011 into the register 12 in step 1 and simultaneously writes the data to the register 15 of the memory 13 using the write command WRITE (A). As a result, the same representative data is written into the registers 12 and 15.

In step 2, the controller 10 performs an exclusive OR operation on the write data 1010 and the representative data 1011, and sends 0001 to the memory 13 through the data bus 16 as a result of the operation. The write command at this time is WRITE (B). In the memory 13, an exclusive OR operation is performed between the data 0001 received now and the representative data 1011, and the result 1010 is written into the memory core.

In the same manner, steps 3 and 4 are performed as follows.

Embodiment of Data Input / Output Unit of Memory Corresponding to Second Principle

Fig. 25 is an embodiment of the data input / output section of the memory (corresponding to the memory 13 of Fig. 1 or the memories 13a to 13d shown in Fig. 2) corresponding to the second principle, and is an example in which a write register and a read register are shared. .

The illustrated data input / output unit is a memory core 20, a switch 140, a receiving gate 141, a register 142, an exclusive OR gate (EX-OR2) 143, a multiplexer (MUX2) 144, and a data input / output circuit. 145, an exclusive-OR gate (EX-OR1) 146, and a multiplexer (MUX1) 147.

In the case of transmitting and receiving the representative data, the representative data receiving signal is generated in the memory, the receiving gate 141 is connected, and the multiplexers 143 and 147 select the input A. In addition, the switch 140 is switched by whether writing or reading is performed. At this time, if it is write data, it is received from the data input / output circuit 145, passed through the multiplexer 147 to the memory core 20 as it is, and also sent to and held by the register 142. On the other hand, in the case of read data, the data from the memory core 20 passes through the multiplexer 144, is output from the data input / output circuit 145 as it is, and is sent to and held in the register 142.

When transmitting and receiving inverted bits, two multiplexers 144 and 147 select input B. At this time, if it is write data, it is received from the data input / output circuit 145 and the exclusive logical sum gate 146 takes an exclusive logical sum with the representative data of the register 142. The result of this operation is passed through the multiplexer 147 and sent to the memory core 20. In addition, if it is read data, the exclusive OR gate 143 calculates an exclusive OR between data from the memory core 20 and representative data of the register 142. The result of this operation passes through the multiplexer 144 and is output from the data input / output circuit 145.

Generally, the representative data is almost all sent from the controller 10 to the memories 13a to 13d. However, in order to provide more general purpose, the representative data is controlled from the memories 13a to 13d in the circuit configuration shown in FIG. Also in (10), it is set as the structure which can transmit representative data.

Embodiment of Data Input / Output Unit of Controller Corresponding to Second Principle

Fig. 26 is an embodiment of a data input / output unit of a controller corresponding to the second principle, in which a write register and a read register are shared. In the drawings, the same reference numerals are assigned to the same components as those shown in the aforementioned drawings.

The data input / output section of the illustrated controller includes a chip select circuit 75, a receive control circuit 77, a chip select signal output circuit 84, a multiplexer 115, an internal circuit 150 of the controller, a switch 151, and a register group. Has 160. In addition, the data input / output unit may include an exclusive OR gate (EX-OR) 161, a multiplexer (MUX) 162, a data I / O circuit 163, an exclusive OR gate (EX-OR) 164, and a multiplexer (MUX) 165. Has

The register group 160 includes four register units 161a to 161d corresponding to the four memories 13a to 13d shown in FIG. Each register unit 161a to 161d has a receiving gate 113 and a register 114.

When the representative data is transmitted and received, the representative data receiving signal is generated in the internal circuit 150. The receiving gate 77 puts the receiving gate 113 of one of the register units 161a to 161d corresponding to the chip select signal in the ON state into a connected state. In addition, the multiplexers 162 and 165 select the input A as the representative data receiving signal. The switch 151 is switched by writing or reading. At this time, if it is write data, it is received from the data input / output circuit 163 and is passed through the multiplexer 165 to the internal circuit 150 as it is, and is also sent to the register 114 of the corresponding register unit for holding. do. On the other hand, in the case of read data, the data from the internal circuit 150 passes through the multiplexer 162 and is output from the data input / output circuit 163 as it is, and is sent to and held in the register 114 of the corresponding register unit.                     

When transmitting and receiving inverted bits, two multiplexers 162 and 165 select input B. At this time, if it is write data, it is received from the data input / output circuit 163 and the exclusive logical sum gate 164 takes an exclusive logical sum with the representative data of the register 114. The result of this operation is passed through the multiplexer 165 and sent to the internal circuit 150. In addition, if the read data, the exclusive OR gate 161 calculates an exclusive OR between data from the internal circuit 150 and representative data of the register 114. The result of this calculation passes through the multiplexer 162 and is output from the data input / output circuit 163.

In the device having the circuit configuration shown in FIG. 25 or FIG. 26, when the data of the registers 142 and 160 are inverted due to the influence of power supply noise or the like, representative data is transferred from the controller 10 to the memory. Resend it. In order to prepare for such a case, it is also possible to prepare an instruction (representative data update instruction) in the instruction system only for sending the representative data and updating the contents of the register without accompanying writing.

Embodiment of Data Input / Output Unit of Memory Corresponding to Both First and Second Principles

Fig. 27 is a diagram showing an embodiment of a data input / output unit of a memory corresponding to both the first and second principles of the present invention described above. In FIG. 27, the same reference numerals are given to the same components as those shown in FIG. This memory has two modes of operation mode 1 operating on the first principle and operation mode 2 operating on the second principle.

The reception gate 141 is controlled as a result of the logical operation of the gate control 1 signal, the mode switching signal, and the representative data acquisition signal. This logical operation consists of inverter 167, AND gates 168 and 169, and OR gate 170. The register 142 is reset to a signal obtained by performing a logic operation on the reset signal (or refresh signal) and the mode change signal at the inverter 171 and the AND gate 172. A gate 173 and a latch 174 are provided between the multiplexer 147 and the memory core 20. The gate 173 is controlled as a result of the OR operation of the mode switch signal and the gate control 2 signal at the OR gate 165. A gate 175 and a latch 176 are provided between the multiplexer 144 and the data input / output circuit 145. The gate 175 is controlled as a result of the OR operation of the mode switch signal and the gate control 3 signal at the OR gate 166. The gate 173, the latch 174, and the gate 175 and the latch 176 are provided to realize an operation corresponding to the operation mode 1.

The gate control 1 signal, the gate control 2 signal, the gate control 3 signal, the data input / output control signal, the representative data acquisition signal, and the read / write switching control signal are, for example, in an internal circuit (not shown) such as a timing controller of a memory. Is generated. The mode switching signal may be set externally using a mode register or the like, or may be programmed at the time of shipment using a fuse or the like. In addition, if both the operation mode 1 and the operation mode 2 are prepared in the command system, it is also possible to switch and operate at any time by the instruction instruction from the controller.

In the operation mode 1, the mode switching signal is set to the L level. Multiplexers 144 and 147 also select input B. The register 142 is reset with a refresh command. The timing of the gate control 1 signal and the gate control 2 signal at the time of writing in the operation mode 1 has a relationship shown in FIG. 27. After the gate control 2 signal is turned ON and the gate 173 is connected to latch the write data to the latch 174, the gate control 1 signal is turned ON to turn the receiving gate 141 into the connected state to write data. The register 142 is stored. At the time of reading, the gate control 3 signal is turned ON, and the read data is latched to the latch 176, and then the gate control 1 signal is turned ON, and the receiving gate 141 is connected to read the register data. Remember to. The receiving gate 141 is controlled by the gate control 1 signal in this timing relationship, the gate 173 is controlled by the gate control 2 signal, and the gate 175 is controlled by the gate control 3 signal. The operation of the operation mode 1 is substantially the same as the operation of the circuit configuration described with reference to FIG. 20.

In the operation mode 2, the mode switching signal is set at the H level. The receiving gate 1 and the multiplexers 144 and 147 are controlled in accordance with the state of the representative data receiving signal. Gates 173 and 175 are fixed in a connected state. The register 142 is not reset in the refresh instruction. The operation of the operation mode 2 is the same as that of the circuit configuration described with reference to FIG. 25.

When the register 142 is inverted due to power supply noise or the like, the register 142 may be reset in the operation mode 1, and the representative data may be re-received in the operation mode 2 to update the contents of the register 142. .

In addition, in the circuit configuration shown in FIG. 27, the following correspondence is also possible by preparing a register update instruction which performs the same operation as the above-mentioned representative data update instruction also in the operation mode 1. When the contents of the register 142 are updated during use in the operation mode 1, the register 10 sends the register update command and the latest data held in the registers of the controller to the memory as they are. When the memory receives the register update command, the memory temporarily sets the mode switching signal to H and generates a representative data receiving signal. As a result, the contents of the registers of the controller and the memory coincide. Thereafter, the mode switching signal and the representative data receiving signal are set to L, and the operation mode 1 is returned. In other words, even in the operation mode 1, the registers of the controller can be transferred as they are to the registers of the memory 142 without being reset.

In addition, in the configuration shown in FIG. 27, the data input / output unit of the controller corresponding to both the first and the second principles prepares the reception gate 141 and the register 142 for only a few of the memories, and receives the switch 140 and the reception. A circuit in which a selector is provided between the gate 141, between the OR gate 170 and the receiving gate 141, between the OR gate 172 and the register 142, and at the output of the register 142, respectively. It becomes a configuration.

In the above, embodiment and Example of this invention were described. The present invention is not limited to the above embodiments and examples, and various other embodiments and examples are possible within the scope of the present invention.

Hereinafter, a part of the present invention described above is summarized as follows.

(Appendix 1) A register for holding the first information and an information generation circuit for receiving the first signal from the outside to generate the second information, wherein the first signal is a signal indicating the inversion of the first information. And the information generation circuit generates the second information based on the first information and the first signal.

(Supplementary Note 2) A register for holding first information and an information generating circuit for receiving second information and outputting a first signal to the outside, wherein the first signal is equal to the first information held in the register. And a signal based on a logical operation of the second information received by the information generating circuit, the signal representing an inversion of the first information.

(Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the information generating circuit rewrites the first information held in the register into the second information.

(Supplementary Note 4) The semiconductor device according to Supplementary Note 1, wherein the information generating circuit receives the first information and stores it in the register, and then receives the first signal to generate the second information.

(Supplementary Note 5) The semiconductor device according to Supplementary Note 1 or 2, wherein the information generating circuit receives the first information and stores it in the register, and then receives the second information to generate the first signal.

(Supplementary Note 6) The semiconductor device according to Supplementary Note 1 or 2, wherein the register is reset by a reset signal.

(Supplementary Note 7) The semiconductor device according to Supplementary Note 1 or 2, wherein the semiconductor device is a semiconductor device including a memory array, and the register is reset based on a refresh instruction received from the outside.                     

(Supplementary Note 8) The semiconductor device according to Supplementary Note 1 or 2, wherein the first signal is a pulse signal.

(Supplementary Note 9) The information generating circuit has a data input section for latching the first signal,

The semiconductor device has a circuit for receiving a chip select signal from the outside,

The semiconductor device according to Appendix 1, wherein the data input unit latches the first signal based on the chip select signal.

(Supplementary Note 10) The semiconductor device according to Appendix 9, wherein the first signal is a pulse signal, and the data input unit detects an edge of the pulse signal to latch the first signal.

(Appendix 11) The information generation circuit has a data input section for latching the first signal,

The semiconductor device has a clock generator for receiving a clock from the outside to generate an internal clock,

The semiconductor device according to Appendix 1, wherein the data input unit latches the first signal in synchronization with the internal clock.

(Appendix 12) The information generation circuit has a data input section for latching the first signal,

The semiconductor device has a clock generator for receiving a clock from the outside to generate an internal clock,

The semiconductor device according to Appendix 1, wherein the data input unit detects and latches an edge of the first signal which is a pulse signal in a predetermined period based on the internal clock.

(Supplementary Note 13) The semiconductor device according to Appendix 1, wherein the semiconductor device is a controller that controls the semiconductor memory device, and resets the register in association with issuance of a refresh instruction to the semiconductor memory device.

(Supplementary Note 14) The semiconductor device according to Supplementary Note 1 or 2, wherein the semiconductor device has an interface that can be selectively connected to a plurality of semiconductor devices, and the register is provided for each of the plurality of semiconductor devices.

(Supplementary Note 15) The semiconductor device according to Supplementary Note 1, wherein the information generating circuit generates the second information by performing an exclusive OR operation on the first information and the first signal.

(Supplementary Note 16) The semiconductor device according to Supplementary Note 2, wherein the information generating circuit generates the first signal by performing an exclusive OR operation on the first information and the second information.

(Appendix 17) A system having a semiconductor device according to Appendix 1 and a semiconductor device according to Appendix 2, wherein each register holds the same first signal.

(Appendix 18) A step of holding the first information in a register;

Generating second information based on the first signal received from the outside and the first information, and transmitting the second information to a predetermined signal line;

And the first signal is a signal representing inversion of the first information.

(Appendix 19) A step of holding first information in a register;

Generating a first signal by performing a logical operation on the received second information and the first information, and transmitting the result to the outside;                     

And the first signal is a signal representing inversion of the first information.

(Supplementary note 20) The information processing method according to supplementary note 18 or 19, wherein the information processing method further rewrites the first information held in the register into the second information.

As described above, according to the present invention, since the inverted bits are configured to be exchanged between the semiconductor devices, waste of information amount is eliminated and power consumption can be reduced.

Claims (24)

In a semiconductor device that exchanges a data series with an external device, A register for storing a first data item of the data string, wherein the first data item precedes immediately before a second data item of the data string; An exchange circuit for exchanging a signal outside of the semiconductor device and a signal indicating which bit or bits of the first data item should be inverted to convert the first data item to the second data item, wherein the signal And a data input unit for latching a signal, for exchanging the signals to achieve exchange of the data strings; And A clock generation unit generating an internal clock in response to a clock received from the outside of the semiconductor device A semiconductor device comprising a. The method of claim 1, And the switching circuit generates the second data item in response to a signal received from the outside of the semiconductor device, and sends the second data item to an internal circuit of the semiconductor device. The method of claim 1, And the exchange circuit generates the signal in response to the second data item received from an internal circuit of the semiconductor device, and sends the signal to the outside of the semiconductor device. The method of claim 1, And the exchange circuit replaces the first data item stored in the register with the second data item. The method of claim 2, And the switching circuit stores the first data item in the register when the first data item is received, and generates the second data item when the signal is received. The method of claim 3, And the switching circuit stores the first data item in the register when the first data item is received and generates the signal when the second data item is received. The method of claim 1, And the register is reset in response to a reset signal. The method of claim 1, The semiconductor device further includes a memory array, And the register is reset in response to a refresh command received from outside of the semiconductor device. The method of claim 1, And the signal is a pulse. The method of claim 2, The exchange circuit includes a data input unit to latch the signal, The semiconductor device further includes a circuit for receiving a chip select signal from the outside of the semiconductor device, And the data input unit latches the signal in response to the chip select signal. The method of claim 10, The signal is a pulse, And the data input unit latches the signal in response to an edge of the pulse. The method of claim 1, And the data input unit latches the signal in synchronization with the internal clock. The method of claim 1, And the data input unit latches the signal in response to a pulse edge of the signal for a predetermined period defined for the internal clock. The method of claim 3, And the semiconductor device is a controller that controls the semiconductor memory device and resets the register with respect to the refresh command when sending a refresh command to the semiconductor memory device. The method of claim 1, The semiconductor device further includes an interface for selectively providing a connection with a plurality of semiconductor devices, And the register is provided for each of the plurality of semiconductor devices. The method of claim 2, And the switching circuit generates the second data item by performing an Exclusive-Or operation of the first data item and the signal. The method of claim 3, And the exchange circuit generates the signal by performing an exclusive OR operation of the first data item and the second data item. In the system comprising the semiconductor device of claim 2 and the semiconductor device of claim 3, And wherein the register of the semiconductor device of claim 2 and the register of the semiconductor device of claim 3 store the same first data item. In the method of exchanging a data series with the outside of the device, Storing a first data item of the data string in a register, wherein the first data item precedes immediately before a second data item of the data string; And Exchanging a signal external to the device and a signal indicating which bit or bits of the first data item should be inverted to convert the first data item to the second data item, wherein the signal exchange The signal exchange step of achieving exchange of the data strings Data heat exchange method comprising a. The method of claim 19, And the second data item is generated by performing a logical operation between a signal received from the outside of the device and the first data item in the register. The method of claim 19, And the signal is generated by performing a logical operation between a second data item received from the outside of the device and the first data item in the register. The method of claim 19, Replacing the first data item stored in the register with the second data item. In a semiconductor device for processing data streams that are continuously input, A register holding first information having a predetermined length included in the data string; An information generating circuit which receives the first signal from the outside and generates second information; And Circuit for receiving chip select signal from outside And The information generation circuit has a data input section for latching the first signal, The data input unit latches the first signal based on the chip select signal, The first signal compares the first information held in the register with third information having a length equal to the predetermined length subsequent to the first information in the data string, wherein the first one of the third information is compared. 1 is a signal indicating that the information is inverted, And the information generation circuit generates the second information based on the first information and the first signal and rewrites the first information held in the register as the second information. In a semiconductor device for processing data streams that are continuously input, A register holding first information having a predetermined length included in the data string; And An information generation circuit for receiving second information having a length equal to the predetermined length following the first information in the data string and outputting a first signal to the outside; The first signal is a signal based on a logical operation of the first information held in the register and the second information received by the information generating circuit. The first signal is a portion of the second information in which the first information is inverted. Is a signal that indicates And the information generation circuit receives the first information from the outside and stores the first information in the register, and then receives the second information to generate the first signal.

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