KR960005871A

KR960005871A - Multi-layer metal wiring formation method of semiconductor device

Info

Publication number: KR960005871A
Application number: KR1019940016476A
Authority: KR
Inventors: 김용권
Original assignee: 문정환; 금성일렉트론 주식회사
Priority date: 1994-07-08
Filing date: 1994-07-08
Publication date: 1996-02-23

Abstract

본 발명은 반도체 소자의 다층금속 배선에 관한 것으로, 특히 서브 마이크로(submi-cron)이하의 집적도를 갖는 디바이스(device)에 적당하도록 한 금속다층 배선형성방법에 관한 것이다. 이를 위한 본 발명의 반도체 소자의 다층금속 배선형성방법은 반도체 기판상에 제1금속층, 제1도전층, 제2금속층을 차례로 형성하는 제1공정, 상기 전면에 절연막을 증착하고 상기 제2금속층과 형성될 제3금속층의 접촉을 위해 배선용 콘택 홀을 형성하는 제2공정, 상기 배선용 콘택홀을 통해 제3금속층을 형성하는 제3공정, 상기 전면에 제2도전층, 제4금속층, 제3도전층을 차례로 형성하는 제3공정을 포함하여 이루어짐을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to multilayer metallization of semiconductor devices, and more particularly to a method for forming a metal multilevel interconnection that is suitable for a device having an integration degree of submi-cron or less. The multi-layer metal wiring forming method of the semiconductor device of the present invention for this purpose is a first step of sequentially forming a first metal layer, a first conductive layer, a second metal layer on a semiconductor substrate, by depositing an insulating film on the front surface and the second metal layer and A second step of forming a wiring contact hole for contacting the third metal layer to be formed; a third step of forming a third metal layer through the wiring contact hole; a second conductive layer, a fourth metal layer, and a third conductive on the front surface And a third step of sequentially forming the layers.

Description

Multi-layer metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 반도체 소자의 다층금속 배선형성 공정단면도이다.3 is a cross-sectional view of a process for forming a multi-layer metal wiring of a semiconductor device of the present invention.

Claims

A first process of sequentially forming a first metal layer, a first conductive layer, and a second metal layer on a semiconductor substrate, depositing an insulating film on the front surface, and forming a contact hole for wiring to contact the second metal layer and the third metal layer to be formed. And a third step of forming a third metal layer through the wiring contact hole, and a third step of sequentially forming a second conductive layer, a fourth metal layer, and a third conductive layer on the front surface. The multilayer metal wiring formation method of a semiconductor element.

The method of claim 1, wherein the second metal layer is formed by contacting aluminum with a sputtering process and the third metal layer is contacted with each other by an MOCVD process.

The method of claim 1 or 2, wherein the thickness of the second metal layer is 200 to 1000 mW.

The method of claim 2, wherein the MOCVD process of the third metal layer is a TIBA of 1 to 20 (cmcm) at a temperature of 180 to 300 ℃, pressure of 50 to 500 millitorr (mcm) A method of forming a multilayer metal interconnection of a semiconductor device, characterized in that it is selectively pyrolyzed to form a positive amount.

※ Note: The disclosure is based on the initial application.