KR960005861A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

Info

Publication number
KR960005861A
KR960005861A KR1019940016972A KR19940016972A KR960005861A KR 960005861 A KR960005861 A KR 960005861A KR 1019940016972 A KR1019940016972 A KR 1019940016972A KR 19940016972 A KR19940016972 A KR 19940016972A KR 960005861 A KR960005861 A KR 960005861A
Authority
KR
South Korea
Prior art keywords
cell
peripheral circuit
semiconductor device
mask
capacitor
Prior art date
Application number
KR1019940016972A
Other languages
Korean (ko)
Other versions
KR0128834B1 (en
Inventor
최양규
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940016972A priority Critical patent/KR0128834B1/en
Publication of KR960005861A publication Critical patent/KR960005861A/en
Application granted granted Critical
Publication of KR0128834B1 publication Critical patent/KR0128834B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히, 캐패시터 플래이트 형성후 감광막을 제거하기 전에 선택적 산화막을 증착시켜 반도체 소자의 고집적화와 디자인 룰의 감소로 인한 셀과 주변회로와의 단차 차이를 줄여 평탄화 시킴으로써 금속 배선 형성시, 사진 식각 공정이 매우 쉬워지고, 금속층의 신뢰성을 높일 수 있게 한 반도체 소자 제조 방법이다.The present invention relates to a method of fabricating a semiconductor device, and in particular, by depositing a selective oxide film after removing the capacitor plate and removing the photoresist, thereby flattening the gap between the cell and the peripheral circuit due to the high integration of the semiconductor device and the reduction of design rules. It is a semiconductor device manufacturing method which makes the photolithography process very easy at the time of metal wiring formation, and can raise the reliability of a metal layer.

Description

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 내지 제4도는 본 발명의 반도체 소자 제조 방법에 따른 공정단계를 도시한 단면도.1 to 4 are cross-sectional views showing the process steps according to the semiconductor device manufacturing method of the present invention.

[발명의 명칭][Name of invention]

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히, 선택적 산화막을 이용하여 반도체 소자의 고집적화와 디자인 룰의 감소로 인한 셀과 주변회로와의 단차 차이를 줄여 평탄화 시키는 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of fabricating a semiconductor device by reducing a step difference between a cell and a peripheral circuit due to high integration of a semiconductor device and a reduction in design rules by using a selective oxide film.

반도체 소자가 초고집적화 경향으로 발전하면서 디자인 룰의 감소로 셀과 주변회로의 단차 차이는 심각하게 증가한다.As semiconductor devices develop into a high integration trend, the gap between the cell and the peripheral circuit increases significantly due to the reduction of design rules.

디램(DRAM) 소자의 경우, 디자인 룰의 감소로 셀의 사이즈는 현저히 작아지고, 작아진 상태에서 충분한 캐패시터 용량을 확보하기 위해 높이는 높아지고, 또한, 다른 배선라인의 경우에서도 선폭의 감소로 전체 단차비(Aspect Ratio)는 증가하게 되므로 셀과 주변회로의 단차증가는 필연적이다.In the case of DRAM devices, the size of the cell is considerably smaller due to the reduction of design rules, the height is increased to ensure sufficient capacitor capacity in the small state, and the overall step ratio is reduced due to the reduction of the line width in the case of other wiring lines. As the aspect ratio increases, the step difference between the cell and the peripheral circuit is inevitable.

이러한 높은 단차는 금속 배선층 형성에 큰 장애요인이 되며, 신뢰성에 치명적인 영향을 주게되는 문제점이 있다. 따라서, 본 발명은 상기의 문제점을 해결하기 위하여 셀과 주변회로를 구분하는 마스크를 써서 셀을 디파인(Define)하고 감광막을 제거하기 전 선택적 산화막(Selective Oxide)을 증착시켜 셀과 주변회로의 단차를 평탄화 시키는 반도체 소자 제조 방법을 제공함에 그 목적이 있다.This high step is a big obstacle to the formation of the metal wiring layer, there is a problem that has a fatal effect on the reliability. Accordingly, in order to solve the above problem, the present invention uses a mask that separates a cell from a peripheral circuit to define a cell and deposit a selective oxide before removing the photoresist layer, thereby reducing the step between the cell and the peripheral circuit. It is an object of the present invention to provide a method for manufacturing a semiconductor device to planarize.

반도체 소자의 제조 방법Manufacturing Method of Semiconductor Device

Claims (4)

실리콘 기판 상부에 여러 소자들을 만들어 셀부와 주변 회로부를 형성하는 단계와, 플래이트를 형성하기 위해 셀부에만 감광막이 있도록 마스크 공정후 식각을 하는 단계와, 캐패시터 플래이트 감광막을 제거하기 전에 선택적 산화막을 증착하는 단계와, 감광막을 제거하는 단계와, 전체 상부에 금속 배선층 형성을 위해 평탄화 산화 절연막으로 도포하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.Forming a cell part and a peripheral circuit part by making a plurality of elements on the silicon substrate, etching after the mask process so that only the cell part has a photoresist film to form a plate, and depositing a selective oxide film before removing the capacitor plate photoresist film And removing the photoresist film and applying the planarized oxide insulating film over the whole to form a metal wiring layer. 제1항에 있어서, 상기 선택적 산화막의 두께를 조절하여 셀부와 주변회로와의 단차를 완화 시키는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1, wherein the step between the cell portion and the peripheral circuit is alleviated by adjusting the thickness of the selective oxide film. 제1항에 있어서, 별도의 마스크를 쓰지 않고 캐패시터 플래이트 형성을 위해 이미 만들어진 감광막을 이용하여 선택적 산화막이 캐패시터가 없는 주변회로부에만 증착되도록 하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1, wherein the selective oxide film is deposited only on the peripheral circuit portion without the capacitor by using a photoresist film that has already been formed to form a capacitor plate without using a separate mask. 제1항에 있어서, 상기 캐패시터 마스크 대신 셀 마스크를 사용하여 셀과 주변회로의 단차를 완화시키는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1, wherein a cell mask is used instead of the capacitor mask to alleviate the step difference between the cell and the peripheral circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940016972A 1994-07-14 1994-07-14 Method for making a semiconductor device KR0128834B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940016972A KR0128834B1 (en) 1994-07-14 1994-07-14 Method for making a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940016972A KR0128834B1 (en) 1994-07-14 1994-07-14 Method for making a semiconductor device

Publications (2)

Publication Number Publication Date
KR960005861A true KR960005861A (en) 1996-02-23
KR0128834B1 KR0128834B1 (en) 1998-04-07

Family

ID=19387976

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940016972A KR0128834B1 (en) 1994-07-14 1994-07-14 Method for making a semiconductor device

Country Status (1)

Country Link
KR (1) KR0128834B1 (en)

Also Published As

Publication number Publication date
KR0128834B1 (en) 1998-04-07

Similar Documents

Publication Publication Date Title
KR950000660B1 (en) Fine patterning method for high density integrated circuit device
KR100359780B1 (en) Method for Fabricating of Semiconductor device
JPH05136132A (en) Method for alleviating step in multilayered structure of semiconductor element and semicon- for alleviating step in multilayered structure
KR100368569B1 (en) Semiconductor device and its manufacturing method
KR960005861A (en) Manufacturing Method of Semiconductor Device
US5466640A (en) Method for forming a metal wire of a semiconductor device
US5494839A (en) Dual photo-resist process for fabricating high density DRAM
KR100964116B1 (en) Method for fabricating of semiconductor device
KR100239450B1 (en) Method for manufacturing of semiconductor device
KR100515008B1 (en) Method for fabricating complex semiconductor device
KR0165491B1 (en) Semiconductor memory device having dumy pattern & its fabrication method
US6645804B1 (en) System for fabricating a metal/anti-reflective coating/insulator/metal (MAIM) capacitor
KR19990012265A (en) Method for manufacturing a DRAM and logic device using an epi layer to suppress the step difference in the cell region
KR100400256B1 (en) Method for fabricating of semiconductor memory device
KR100244408B1 (en) Manufacture of semiconductor device
KR100333653B1 (en) Method for forming wiring in semiconductor device
KR19990012665A (en) Knock Control Method for Correction of Learning Value by Driving Area
KR930022553A (en) DRAM with bitline contacts and capacitor contacts
KR100192369B1 (en) A plannerizing method in the semiconductor process
KR960002781B1 (en) Method of making a capacitor of dram memory cell
KR0124487B1 (en) Fine contact forming method of semiconductor device
KR100357174B1 (en) Method for fabricating capacitor of semiconductor device
US5728597A (en) Method for forming a capacitor in a semiconductor device
JP3166749B2 (en) Semiconductor device and method of manufacturing the same
JPS62281328A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091028

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee