KR960005563B1 - Method for manufacturing a mask rom using polysilicon island - Google Patents

Abstract

forming an isolation layer(14) and gate oxide layer(11) on a semiconductor substrate(18) to define an active region(19), and forming a gate electrode(10) on the gate oxide layer and a first interlevel insulating layer(17) on the substrate; selectively etching the first interlevel insulating layer(17) to expose the gate electrode(10); forming a contact hole for the purpose of programming of ROM data, a word line(15) in the contact hole, and a second interlevel insulating layer(17') on the word line(15), selectively etching the first and second interlevel insulating layers(17,17') to form a contact hole; and forming a bit line(16) to contact with the active region through the contact hole.

Description

Mask ROM Manufacturing Method Using Polysilicon Island

1 is a mask ROM forming diagram according to a conventional embodiment;

2 is a mask ROM forming diagram according to another conventional embodiment;

3 is a plan view of a rom cell according to the present invention,

4 is an equivalent circuit diagram for FIG. 3,

5 and 6 are manufacturing process diagrams of the present invention along the word and bit lines of FIG. 3, respectively.

* Explanation of symbols for main parts of the drawings

10 Irish type gate electrode 11 Gate oxide film

14 element isolation insulating film 16 bit line

17, 17 ': insulating film 18: semiconductor substrate

19: active area

12: Contact between gate island and word line (program contact)

15: word line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mask ROM (ROM), and more particularly to a method of manufacturing mask ROM using polysilicon islands.

Referring to FIG. 1 and FIG. 2, a conventional method for fabricating a mask ROM is described in detail with reference to FIGS. 1 and 2. Silver bit lines, 17 and 17 'are insulating films, 18 are semiconductor substrates, and 19 are active regions, respectively.

First, an embodiment of the present invention will be described in detail with reference to the cross-sectional view of FIG. 1. FIG. 1 shows a semiconductor device 18 having a predetermined size of a device isolation insulating film 14, a gate oxide film 11, a gate electrode 15, n ⁺ active region 19 is formed to form a depletion-type MOSFET, and then ion implantation into a specific transistor by high energy ion implantation through the gate electrode 15 and gate oxide film 11 at the request of the purchaser. This is a cross-sectional view of the mask ROM in which the insulating film 17 is applied, the contact hole 13 is formed, and the bit line 16 is brought into contact with the active region 19 after switching to the increment transistor.

However, the conventional mask ROM has a drawback that the reliability of the cell transistor is reduced due to the high energy ion implantation, and the program characteristics are sensitively affected by the process change.

In addition, referring to FIG. 2, another conventional embodiment is formed by selectively forming notched polygates (US Pat. App. No. 4,410,904) of a specific cell using a polysilicon mask when forming a polysilicon gate of a cell transistor. It is a program method that connects source and drain.

This method also has a problem in that the manufacturing process is long in the ROM process side that should shorten the process period after the program by the orderer.

The present invention devised to solve the above problems is to provide a method for manufacturing a mask rom using a polysilicon island that can secure the reliability of the device and significantly shorten the process period.

In order to achieve the above object, the present invention provides a first step of forming a semiconductor substrate element isolation insulating film and a gate oxide film, forming a gate electrode and an active region to a predetermined size, and applying an interlayer insulating film, and then programming the characteristic cell after the first step. A second step of forming a contact hole by etching a portion of the first interlayer insulating layer to form a selective contact with the formed gate island using a contact mask, and depositing a word line to a predetermined size in the contact hole, and the second step After the third step, a second interlayer insulating film is coated to insulate the word line, and the first and second interlayer insulating films are etched to a predetermined size to form a contact hole, and then a bit line is deposited to contact the active region. And a fourth step of making contact with the active region.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the attached drawings 3 to 6, FIG. 3 is a plan view of a ROM cell according to the present invention, FIG. 4 is an equivalent circuit diagram of FIG. 3, 5 and 6 are manufacturing process diagrams of the present invention along the word and bit lines of FIG. 3, respectively, in which 17 'represents an interlayer insulating film.

First, FIG. 3 shows four cells. In the case of cell B, a cell having no polyline and word lines connected to an island, that is, a cell not programmed, and a cell connected to a word line, i.e., a contact, It is shown in detail in Figure 4 which is a cell programmed by it, an equivalent circuit diagram thereof.

Each cell is composed of an incremental MOSFET, and when a sufficient potential is applied to the word line to lead the cell, the cell of the gate 10 joined to the word line is turned on (A cell) and the unconnected cell ( Cell B) is turned off to read data.

A method of fabricating a mask rom which realizes the present invention having such a structure will be described in detail with reference to sectional views along two directions of the bit line direction shown in FIG. 5 and the word line direction shown in FIG.

First, FIGS. 5A and 6A are cross-sectional views in which the device isolation insulating film 14 and the gate oxide film 11 are formed on the semiconductor substrate 18.

5 (b) and 6 (b) are cross-sectional views of the gate electrode 10 and the active region 19 formed in a predetermined size, and the interlayer insulating film 17 is coated.

5 (c) and 6 (c) show a contact hole by etching a portion of the first interlayer insulating layer 17 to form a selective contact with the formed gate 14 and forming a word line 15 in the contact hole. ) Is a cross-sectional view of a state of depositing a certain size (that is, the program is made depending on the presence or absence of a contact hole).

5 (d) and 6 (d) show a second interlayer insulating film 17 'for insulating the word line 15 and first and second contacts for contact with the active region 19, respectively. The interlayer insulating layers 17 and 17 'are etched to predetermined sizes to form contact holes, and then the bit lines 16 are deposited to make contact with the active region 19.

According to the present invention as described above, a process of manufacturing a program is simple because a selective contact hole between a polygate island and a word line is formed to form a program, and damage to a substrate such as high energy ion implantation does not occur. In addition to increasing reliability, the program formation takes place in the final stage, which is an excellent effect on mask ROM fabrication, which can significantly shorten the period.

Claims (1)

In a method of manufacturing a mask ROM using a polysilicon island, a device isolation insulating film 14 and a gate oxide film 11 are formed on a semiconductor substrate 18, and a gate electrode 10 and an active region 19 are formed to a predetermined size. A first step of applying the interlayer insulating film 17, and after the first step, the first interlayer insulating film 17 to form a selective contact solution with the formed gate 10 using a contact mask for the purpose of programming ROM data. Etching a portion to form a contact hole and depositing a word line 15 to a predetermined size in the contact hole, and a second interlayer insulating layer 17 for insulating the word line 15 after the third end. ') Is coated and the second and second interlayer insulating films 17 and 17' are etched to a predetermined size to form a contact hole, and then the bit lines 16 are deposited to make contact with the active region 19. The fourth step of making contact with the active region 19 is Mask ROM manufacturing method using a polysilicon island, characterized in that provided.