KR960005376B1 - Output circuit - Google Patents

Abstract

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Description

Output circuit

1 is a circuit diagram of a conventional output circuit of the analog drive type.

2 is a circuit diagram showing an output circuit according to an embodiment of the present invention.

3 is a circuit diagram showing an output circuit according to another embodiment of the present invention.

4 is a circuit diagram showing an output circuit according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11: differential amplifier Q30: first NPN transistor

Q31: 2nd PNP transistor Q32: 3rd NPN transistor

Q23, Q24, Q33: PNP Transistor Q21, Q22, Q35: NPN Transistor

Q34: NPN transistor for pull-up Q36: NPN transistor for pull-down

I, I1, I2: current source Vo: output voltage

Vcc: power supply voltage T1: input terminal

T2: Output stage

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more particularly, to an output circuit used at an output stage requiring a large current and a large output amplitude such as a motor driving circuit.

[Traditional Technology and Problems]

In general, a switched output circuit or an analog driven output circuit is used as an output circuit at an output terminal of a brushless motor driving circuit, and since the electrical noise is generated in the switched output circuit, such an electrical A large capacity capacitor is required to smoothly drive the brushless motor while lowering the noise. Therefore, the switching type output circuit needs to provide a large capacity capacitor, which is not suitable for miniaturization and cost. Therefore, in order to avoid the above drawbacks, analog drive type output circuits are widely used.

FIG. 1 is a circuit diagram showing an example of an analog drive type output circuit. In this analog drive type output circuit, a pull-up NPN transistor Q10 and a pull-down NPN transistor Q12 are differential amplifiers. When the input current is not supplied to the input terminal T1, the diodes D1 to D4 and the transistors Q8 to Q11 are controlled to control the current of the pull-up NPN transistor Q10. A loop made of a will be formed. That is, the current flowing to the pull-up NPN transistor Q10 is controlled by the change of the emitter region of each transistor, and if a positive input current Ii + is supplied to the input terminal T1, a differential amplifier ( 11) In the non-inverting input terminal (+) of

Vin = Verf + (Ii +) x R2 ----------------------- (1)

It becomes Here, Verf represents a reference voltage supplied to the reference stage of the differential amplifier 11.

Therefore, since the output signal of the differential amplifier 11 is output as a high level, the current supplied by the current mirror circuit composed of the current source I and the PNP transistors Q5 and Q6 is the base of the pull-up NPN transistor Q9. Supplied to an electrode, from which the pull-up NPN transistors Q9 and Q10 are turned on. In this state, the pull-down PNIP and NPN transistors Q11 and Q12 are turned off. At that time, when a negative current Ii- flows from the input terminal T1, the input voltage Vin at the non-inverting input terminal (+) of the differential amplifier 11 is

Vin = Verf-(Ii-) x R2 ----------------------- (2)

It becomes Accordingly, since the output signal of the differential amplifier 11 is output as a low level, in this state, the pull-down PNP and NPN transistors Q11 and Q12 are turned on while the pull-up NPN transistors Q9 and Q10 are turned off, respectively. As a result, an amplifying circuit is formed as a whole of the circuit. Here, the relationship between the input current Ii and the output voltage Vo of the amplification circuit

R2Ii = R3, Vo / (R3 + R4) -------------------- (3)

Therefore, the gain G of this amplifier circuit is

G = Vo / R2Ii = R2 (R3 + R4) / R3 -------------- (4)

It becomes

At this time, if R2 = R3, the gain G of this amplifier circuit is

G = R3 + R4 ----------------------------- (5)

Where R2, R3, and R4 represent resistance values of the resistors R2, R3, and R4, respectively.

In this way, an analog drive type output circuit for supplying a large amplified output voltage and a large current can be realized, thereby preventing electrical noise generated by a conventional switching type output circuit and obtaining a stable output waveform. Will be. Moreover, a sufficient output current is obtained as shown below.

Ic10 = Ic6 xh _fe 9 xh _fe 10 ---------------------- (6)

Ic12 = Ic7 xh _fe 8 xh _fe 12 ---------------------- (7)

Where Ic10 and Ic12 represent the collector currents of the NPN transistors Q10 and Q12 for pull-up and pull-down, and h _fe 8, h _fe 9, h _fe 10 and h _fe 12 represent NPN transistors Q8, Q9, Q10 and Q12, respectively. ) Represents the current gain.

Therefore, in saturation state, the maximum output voltage Vmax of the output terminal T2 is

Vmax = Vcc = Vbe10-Vbe9-Vces6 ------------- (8)

Where Vces6 represents the voltage between the collector-emitter of the PNP transistor Q6 while the PNP transistor Q6 is saturated. In addition, the minimum output voltage (Vmin) of the output terminal (T2) in saturation state

Vmin = Vces12 --------------------------- (9)

Where Vces12 represents the voltage between the collector-emitter of the pull-down NPN transistor Q12 when the pull-down NPN transistor Q12 is saturated.

On the other hand, Vbe and Vces are about 0.7 (V) and 0.3 (V), respectively, and the maximum output voltage (Vmax) is lowered by about 1.7 (V) with respect to the power supply voltage (Vcc). Recently, the demand for lowering the power supply voltage (Vcc) has become more stringent. For example, in the floppy disk drive circuit, it is necessary to operate the output circuit with the power supply voltage (Vcc) of 5V, so that the output can be sufficiently driven. There is a need for an output circuit that can supply current and output voltage amplitude or as much torque as possible.

[Purpose of invention]

The present invention has been made in view of the above, and an object thereof is to provide an analog drive type output circuit capable of increasing the output amplitude of the output circuit and supplying a large output amplitude and a large current.

[Configuration of Invention]

The present invention for achieving the above object, the first and second power potential supply means for supplying the first and second power potential, respectively, the output terminal for outputting the output signal, respectively, the base electrode and collector electrode and Emmy A first conductive type first transistor having a emitter electrode, a second conductive type second transistor having a base electrode, a collector electrode, and an emitter electrode, respectively, a first conductive type third having a base electrode, a collector electrode, and an emitter electrode, respectively Input signal supply means for supplying an input signal to a transistor, base electrodes of the first and second transistors, bias voltage supply means for supplying a bias voltage to the base electrode of the third transistor, and second power potential supply means A current source for connecting the emitter electrodes of the first and third transistors, and the emitter electrodes of the second transistor are connected to the first power potential supply means. Connecting means for connecting the collector electrode of the third transistor while the first transistor is connected, a first output transistor means for supplying the amplified current to the output terminal while amplifying the collector current of the first transistor, and the collector current of the second transistor. And a second output transistor means for supplying the amplified current to the output terminal while amplifying the output terminal.

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating an output circuit according to an exemplary embodiment of the present invention, in which the first NPN transistor Q30 and the second NPN transistor Q31 are connected to the output terminal of the differential amplifier 11 so that the differential amplifier 11 is connected. The output signal of is supplied. The emitter electrode of the first NPN transistor Q30 is connected to the emitter electrode of the third NPN transistor Q32, and the emitter electrodes of the first and third NPN transistors Q30 and Q32 are commonly connected to each other. It is connected to the ground terminal GND via I1. In addition, while the emitter electrode of the second NPN transistor Q31 is coupled to the power supply voltage Vcc via the diode D10, the collector electrode is connected to the base electrode of the sixth NPN transistor Q35, and the sixth NPN transistor The collector electrode of Q35 is connected to the power supply voltage Vcc and its emitter electrode is connected to the base electrode of the pull-down NPN transistor Q36. Therefore, the sixth and pull-down NPN transistors Q35 and Q30 are made of Darlington connections.

The collector electrode of the first NPN transistor Q30 is connected to the base electrode of the PNP transistor Q33, and the collector electrode of the PNP transistor Q33 is connected to the power supply voltage Vcc. It is connected to the base electrode of the NPN transistor Q34 for use, and the emitter electrode of the pull-up NPN transistor Q34 is connected to the output terminal T2. One end of the resistor R5 is connected to the cathode electrode of the diode D10, and the other end thereof is connected to the ground terminal GND via the base electrode of the third NPN transistor Q32 and the current source I2. Accordingly, the resistor R5 and the current source I2 form a bias circuit with respect to the third NPN transistor Q32.

On the other hand, the differential amplifier 11 has an inverting input terminal (-) and a non-inverting input terminal (+), and these input terminals are supplied with reference voltages Vref through the resistors R2 and R3, respectively. The inverting input terminal (+) is connected to the input terminal T1 to supply an input current, and the inverting input terminal (-) is connected to the output terminal T2 via the feedback resistor R4. In the circuit, the pull-up NPN transistor Q34 and the pull-down NPN transistor Q36 are operated by the first NPN transistor Q30 and the second NPN transistor Q31, and the first NPN and second NPN transistors Q30 and Q31. The output signal of the differential amplifier 11 is supplied to the base electrode. At this time, when a positive input current Ii + is supplied to the input terminal T1, the input voltage Vin at the non-inverting input terminal (+) of the differential amplifier 11 is

Vin = Verf + (Ii +) x R2 ------------------ (10)

And R2 represents the resistance value of the resistor R2.

In this state, since the output signal of the differential amplifier 11 is output as a high level, the first NPN transistor Q30, the PNP transistor Q33, and the pull-up NPN transistor Q34 are turned on so as to be at a high level at the output terminal T2. In this condition, the second NPN transistor Q31 and the fourth and pull-down NPN transistors Q35 and Q36 are turned off. Accordingly, the conditions for changing the first NPN transistor Q30 to the ON state are as follows. In other words,

V1> Vcc-Vf-I2R5-Vbe32 + Vbe30 -------- (11)

Where

V1; Output voltage of the differential amplifier 11, Vf; Forward voltage of diode D10, I2; The current value of the current source I2, R2; Resistance values of the resistor R2, Vbe30, Vbe32; The voltage between the base and the emitters of the first and third NPN transistors Q30 and Q32 is shown.

In addition, when a negative input current Ii- flows from the input terminal T1, a voltage drop represented by (Ii-) x R2 is applied to the resistor R2, and the voltage drop of the differential amplifier 11 Since the input voltage Vin is lowered at the input terminal T1, the output signal of the differential amplifier 11 is made low.

In this state, when the second NPN transistor Q31 is turned on,

V1 <Vcc-Vf-Vbe31 ------------------- (12)

As can be clearly seen from Eqs. (11) and (12), assuming that the voltages between the base and emitters of the transistors are the same, both the first and second NPN transistors Q30 and Q31 are off. The limit voltage (V) is

V = -I2R5 + Vbe32 --------------------- (13)

It becomes Therefore, by setting the voltage Vbe32 larger than I2 and R5, the current flowing through the pull-up NPN transistor Q34 when the input current is not supplied to the input terminal T1 is controlled.

In addition, the diode D10 is required to turn on the first NPN transistor Q30, the PNP transistor Q33, and the pull-up NPN transistor Q34.

Vces30 + Vbe33 <Vbe32 + I2R5 + Vf ---------- (14)

Where Vces30 is the voltage between the collector-emitter when the first NPN transistor Q30 is saturated, and Vbe33 is the voltage between the base-emitter of the PNP transistor Q33.

Since the PNP transistor Q33 for operating the pull-up NPN transistor Q34 in the circuit is operated by the first NPN transistor Q30, the emitter-collector path of the PNP transistor Q33 and the NPN transistor Q34 for pull-up. The base-emitter path of is only present between the output terminal T2 and the power supply voltage Vcc. Therefore, the maximum output voltage Vmax at the output terminal T2 is

Vmax = Vcc-Vbe34-Vces33 ------------- (15)

Where Vces33 represents the voltage between the collector-emitter of the PNP transistor Q33 in saturation.

In addition, the initial voltage Vmin at the output terminal T2 is

Vmin = Vces36 --------------------- (16)

Where Vces36 represents the voltage between the collector and emitter of the NPN transistor Q36 for pulldown in saturation.

Also, as can be clearly seen from Equations (8) and (15), the output amplitude is increased in comparison with the conventional output circuit, and this increase becomes more important at the low power supply voltage Vcc. Therefore, the collector current of the NPN transistors Q34 and Q36 for pull-up and pull-down

Ie34 = I1 x h_fe33 x h_fe34 -------------(17)Ic34

Ie34 = I1 xh _fe 33 xh _fe 34 ------------- (17)

Ic36 = Ic31 xh _fe 35 xh _fe 36 ---------------- (18)

Since sufficient output current can be obtained, the circuit as a whole forms an amplifying circuit. Here, the relationship between the input current Ii and the output voltage Vo of the amplification circuit

R2Ii = R3Vo / (R3 + R4) -------------- (19)

From which the gain G of the amplification circuit

G = Vo / R2Ii = R2 (R3 + R4) / R3 --------- (20)

It becomes At this time, if R2 = R3, gain (G) of amplification circuit is

G = R3 + R4 ------------------------ (21)

Where R2, R3, and R4 represent resistance values of the resistors R2, R3, and R4, respectively.

By the above method, an analog drive type output circuit for supplying a large amplitude output voltage and a large current is obtained.

3 is a circuit diagram showing an output circuit according to another embodiment of the present invention, in which the differential amplifier 11 includes a current mirror circuit including a pair of NPN transistors Q21 and Q22 and a PNP transistors Q23 and Q24. The resistors R13 to R16 connected to the electrodes between the base and emitters of the transistors Q33, Q34, Q35, and Q36 are employed to avoid malfunctions caused by leakage current.

4 is a circuit diagram showing an output circuit according to another embodiment of the present invention, in which the diodes D13, D14, D15, and D16 are connected in parallel to the resistors R13 to R16, respectively. The addition of diodes D13 to D16 reduces the input current of the transistors Q33 to Q36, thereby reducing the output impedance of the differential amplifier 11, thereby suppressing phase shift in each transistor. Therefore, since local oscillation in each transistor due to the phase shift is suppressed, stable output is obtained.

[Effects of the Invention]

As described above, according to the present invention, by using an analog driving method using a differential amplifier, not only a stable output without noise generation but also a large output amplitude similar to the switching driving method can be obtained.

Claims (8)

First and second power potential supply means (Vcc, GND) for supplying the first and second power potentials, respectively, and an output terminal T2 for outputting an output signal, respectively, a base electrode, a collector electrode, and an emitter electrode. A first conductive type Q transistor having a first conductivity type and a second conductive type Q31 having a base electrode, a collector electrode, and an emitter electrode, and a first conductive type having a base electrode, a collector electrode, and an emitter electrode, respectively. A bias voltage is supplied to a third transistor Q32, an input signal supply means for supplying an input signal to base electrodes of the first and second transistors Q30 and Q31, and a base electrode of the third transistor Q32. A bias voltage supply means, a current source I1 for connecting the emitter electrodes of the first and third transistors Q30 and Q32 to the second power potential supply means GND, and the first power potential supply means. Emmy of the second transistor Q31 at (Vcc) Connecting means for connecting the collector electrode of the third transistor Q32 while connecting the emitter electrode, a first for supplying the amplified current to the output terminal T2 while amplifying the collector current of the first transistor Q30. And an output transistor means and a second output transistor means for supplying the amplified current to the output terminal (T2) while amplifying the collector current of the second transistor (Q31). 2. The apparatus of claim 1, wherein the input signal supply means comprises an automatic amplifier (11) having an inverting input terminal (-) and a non-inverting input terminal (+), and first and second resistors (R2, R3). The input voltages Ii + and Ii- are supplied to the inverting input terminal + while the reference voltage Verf is supplied through the first resistor R2, and the reference voltage is supplied to the inverting input terminal + through the resistor R3. Output circuit, characterized in that the (Verf) is supplied. The method of claim 1, wherein the bias voltage supply means is connected between a first current source (I2) connected to the base electrode of the third transistor (Q32), and between the collector electrode and the base electrode of the third transistor (Q32). An output circuit comprising a resistor (R5). An output circuit according to claim 1, wherein said connecting means is made of a diode (D10). 3. The output circuit according to claim 2, wherein the inverting input terminal (-) of the differential amplifier (11) is connected to the output terminal (T2) via a feedback resistor (R4). 2. The first output transistor means of claim 1, wherein a base electrode is connected to a collector electrode of the first transistor Q30, an emitter electrode is connected to a first power potential supply means (Vcc), and the collector electrode is connected. The second conductive fourth transistor Q33 and the base electrode are connected to the collector electrode of the fourth transistor Q33, and the collector electrode is connected to the first power potential supply means Vcc. And a fifth transistor Q34 connected to the output terminal T2, wherein the second output transistor means has a base electrode connected to the collector electrode of the second transistor Q31, and the collector electrode supplies the first power potential. The first conductive sixth transistor Q35 and the base electrode connected to the means Vcc and having the emitter electrode are connected to the emitter electrode of the sixth transistor Q35, and the collector electrode is connected to the output terminal T2. The emitter electrode is connected to the second power supply potential. A first conductivity type connected to a first class unit (GND) 7, characterized in that the output circuit consisting of a transistor (Q36). The method of claim 6, wherein the first output transistor means comprises a fifth resistor (R13) connected between the base of the fourth transistor (Q33) and the emitter electrode, and the base and emitter electrode of the fifth transistor (Q34). The second output transistor means includes a seventh resistor R15 and a seventh transistor Q36 connected between the base of the sixth transistor Q35 and the emitter electrode. And an eighth resistor (R16) connected between the base electrode and the second power potential supply means (GND). The method of claim 7, wherein the first output transistor means of the fifth resistor (R13) and diode (D13) connected between the base electrode and the emitter electrode of the fourth transistor (Q33) and the fifth transistor (Q34) A sixth resistor R14 and a diode D14 connected between the base electrode and the emitter electrode, and the second output transistor means includes a seventh connected between the base electrode and the emitter electrode of the sixth transistor Q35. And an eighth resistor R16 and a diode D16 connected between the resistor R15 and the diode D15, the base electrode of the seventh transistor Q36, and the second power source supply means GND. Output circuit.

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