KR960004084B1 - Multi-layer metal line for semiconductor device - Google Patents

Multi-layer metal line for semiconductor device Download PDF

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Publication number
KR960004084B1
KR960004084B1 KR92025887A KR920025887A KR960004084B1 KR 960004084 B1 KR960004084 B1 KR 960004084B1 KR 92025887 A KR92025887 A KR 92025887A KR 920025887 A KR920025887 A KR 920025887A KR 960004084 B1 KR960004084 B1 KR 960004084B1
Authority
KR
South Korea
Prior art keywords
forming
film
etching
insulation
exposed
Prior art date
Application number
KR92025887A
Other languages
Korean (ko)
Other versions
KR940016732A (en
Inventor
Keun-Yuk Lee
Sung-Bo Hwang
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Priority to KR92025887A priority Critical patent/KR960004084B1/en
Publication of KR940016732A publication Critical patent/KR940016732A/en
Application granted granted Critical
Publication of KR960004084B1 publication Critical patent/KR960004084B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

forming a first contact hole where a conduction layer is exposed by etching a first insulating film of predetermined part after forming a first insulation layer on top of the conduction layer; forming nitride film after forming a conductive plug on the first contact hole; forming a second contact hole where the conductive plug is exposed by etching the predetermined second insulation film and the bottom nitride film by forming the second insulation film on top of the nitride film; forming metal contact layer on top of a whole structure with a thin width and then thickly depositing tungsten film on top of that; and forming a third insulation film after etching the tungsten film until the upper part of second insulation film is exposed by etching-back the tungsten film.
KR92025887A 1992-12-28 1992-12-28 Multi-layer metal line for semiconductor device KR960004084B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92025887A KR960004084B1 (en) 1992-12-28 1992-12-28 Multi-layer metal line for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92025887A KR960004084B1 (en) 1992-12-28 1992-12-28 Multi-layer metal line for semiconductor device

Publications (2)

Publication Number Publication Date
KR940016732A KR940016732A (en) 1994-07-25
KR960004084B1 true KR960004084B1 (en) 1996-03-26

Family

ID=19347000

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92025887A KR960004084B1 (en) 1992-12-28 1992-12-28 Multi-layer metal line for semiconductor device

Country Status (1)

Country Link
KR (1) KR960004084B1 (en)

Also Published As

Publication number Publication date
KR940016732A (en) 1994-07-25

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