KR960002685B1 - Atm cell discrimination and scrambling by bit unit - Google Patents

Abstract

a transmitting part having a scrambler which scrambles 48 byte payload of 53 bytes cells in byte unit, a parallel HEC(header error control) encoder which receives an initial 4 bytes of 5 bytes cell header in the byte unit to generate the HEC and inserts the generated HEC into the fifth byte, and a transmitting controller which controls the scrambler and the parallel HEC encoder; a receiving part having a parallel HEC reverse encoder which controls a cell boundary extraction and error in a cell header from the data in the byte unit transmitted to a physical medium connector, a reverse scrambler which restores an original cell payload from the scrambled 48 byte payload, and a receiving controller which controls the parallel HEC reverse encoder and the reverse scrambler; and command and state registers each connected to the transmitting controller and the receiving controller.

Description

Byte processing ATM cell boundary identification and mixing processing device

1 is a block diagram of peripheral devices of a cell boundary identification and mixing module to which the present invention is applied.

2 is a block diagram of a cell boundary identification and mixing apparatus according to an embodiment of the present invention.

3 is a timing diagram of a generation signal and an input signal of a transmission control unit according to an embodiment of the present invention.

4 is a block diagram of a self-synchronizing mixer according to an embodiment of the present invention.

5 is a block diagram of a HEC mismatcher according to an embodiment of the present invention.

6 is a timing diagram of an output signal and an output signal of a reception controller according to an exemplary embodiment of the present invention.

7 is a block diagram of a header error control unit according to an embodiment of the present invention.

8 is a block diagram of a self-synchronous inverse mixer in accordance with an embodiment of the present invention.

9 is a block diagram of a HEC state tracking unit according to an embodiment of the present invention.

10 is a configuration diagram of a command register and a status register according to an embodiment of the present invention.

11 is a detailed block diagram of a transmission control unit according to an embodiment of the present invention.

12 is a detailed block diagram of a reception controller according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

21: mixing unit 22: parallel HEC coding unit

23: transmission control unit 24: parallel HEC decoding unit

25: reverse mixing unit 26: reception control unit

27: register 211: self-synchronizing mixer

212,222,273,274,252: Multiplexer

221: HEC mismatcher 241: HEC state tracking unit

242: header error control unit 243: shift register

244: Error Correction 271: Command Register

272: status register

The present invention relates to an apparatus for processing an ATM cell boundary identification and a hybridization function in units of bytes among ATM physical layer functions supporting the ATM protocol.

In the conventional high speed communication network, information transmission is performed by using a synchronous transmission method. In this case, communication is possible by having a simple frame generation and identification function. However, due to the development of communication technology and various demands for high quality services of users, the Broadband Integrated Information Network (BISDN) has emerged. In this case, the information is delivered in the form of cells, and in addition to the existing simple frame generation and identification functions, The ability to blend is needed.

Accordingly, an object of the present invention is to provide a cell boundary identification and mixing apparatus capable of processing ATM cell boundary identification and mixing functions in units of bytes among physical layer functions supporting the ATM protocol.

Another object of the present invention is to reduce the hardware burden by using a header error decoder technique, rather than a table look-up method, which is generally used as a header error control scheme used for cell boundary identification, and to improve all functions. It is an object of the present invention to provide a cell boundary identification and mixing device capable of processing data at the TLL level by processing in units of bytes.

In order to achieve the above object, the present invention provides a mixing means for mixing a 48-byte payload in byte units among 53-byte cells transmitted from a cell rate matching unit, and the first 4 bytes in byte units of a 5-byte cell header. A byte-processing parallel HEC encoding means having a function of receiving and generating HEC (Header Error Control, " HEC ") and inserting it into the fifth byte, and transmitting control of the mixing means and the parallel HEC encoding means. A transmitter having control talk; Byte-processing parallel HEC decoding means for controlling the extraction of cell boundaries and error in cell headers from the byte-based data transmitted from the physical medium connection, and recovering the original cell payload from the mixed 48-byte payload. And a receiving unit having demixing means, a reception control means for controlling the parallel HEC decoding means and the demixing means, and a command register and a status register connected to the transmission control means and the reception control means.

In addition, the present invention divides the ATM cell boundary identification and mixed function into a transmitter and a receiver, and has a merit that it is easy to debug and implement a system by systematically separating and implementing functions within each transceiver.

That is, the transmitter provides a parallel HEC encoding function that has a hybridization function of scrambling a payload of a cell transferred from an upper layer to a physical layer in units of bytes and a function of properly generating and inserting an HEC in a cell header.

The receiver extracts the boundary of the cell from the byte unit data transmitted from the physical medium, detects an error occurring in the cell header, and corrects it in the case of a single bit error. It provides a demixing function to recover the cell payload.

In addition, the command and status registers are placed in the HEC cell boundary identification and intermixing device to provide the physical layer management unit with the ability to perform maintenance, including layer management and loop-back testing.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a physical layer peripheral functional block to which the present invention operates. In the drawing, reference numeral 1 denotes a physical medium connection unit, reference numeral 2 denotes a cell boundary identification and mixing unit according to the present invention, and reference numeral 3 denotes a cell speed matching unit and a code. 4 denotes a layer management connector, and 5 denotes a clock generator.

The cell boundary identification and blending unit 2, which is a functional device according to the present invention, is transmitted from the physical medium access unit 1, which is responsible for the transmission of the actual information through the physical medium, from the user information cell and the physical layer unmanageable through the ATM layer. The cell speed matching unit 3 for proper speed matching using the OAM cell and the effective cell, the layer management connection unit 4 for providing OAM cell delivery and layer management, and restarting, driving the status display LED, and clock timing matching. It is connected to a clock generator 5 that provides a clock for the.

2 is a block diagram of a cell boundary identification and mixing unit 2 according to an embodiment of the present invention, 21 is a mixing unit, 211 is a self-synchronous mixer, 212, 222, 273, 274, 252 is a multiplexer, code 22 is a parallel HEC encoder, code 221 is a HEC submixer, code 23 is a transmission control unit, code 24 is a parallel HEC decode unit, code 241 is a HEC state tracking unit, code 242 is a header error control unit 243 is a shift register, 244 is an error correction unit, 25 is an inverse mixing unit, 26 is a reception control unit, 27 is a register unit, 271 is a command register and 272 status register.

The configuration of the present invention is largely divided into a transmitter and a receiver, as shown in the figure.

The transmitting unit accepts the first four bytes in the byte unit of the five-byte cell header and the mixing unit 21 for mixing the 48-byte payload in byte units among the 53-byte cells transmitted from the cell rate matching unit 3. It consists of a parallel HEC encoder 22 having a function of generating an HEC and inserting it into the fifth byte, and a transmission controller 23 for controlling the transmitter.

The receiver not only extracts the boundary of the cell from the byte unit data transmitted from the physical medium connection unit 1, but also a parallel HEC decoding unit having a function of controlling an error in the cell header (single bit error correction and multiple bit error detection). (24), a demultiplexer 25 for recovering the original cell payload from the mixed 48-byte pairload, and a reception controller 26 for controlling the receiver.

In addition, the instruction register 271 and the status register 171 are placed in the cell boundary identification and mixing unit, and the physical layer management unit is designed to perform maintenance including layer management and loop-back test.

The mixing unit 21 is a self-synchronizing mixer 211 and a multiplexer for processing the polynomial X ⁴³ +1 of the self-synchronizing mixer (SSS) recommended by the CCITT for SDH-based transmission in units of bytes. 212. The signal for controlling the self-synchronizing mixer 211 is generated by the sweep control unit 23. When the MUX SCR signal is '1', the multiplexer 212 transfers the SCR [7: 0], which is the mixed payload data, output from the self-synchronous mixer 211 to the HEC submixer 221.

3 is a timing diagram showing a correlation between a signal generated by the transmission control unit 23 and a signal transmitted by the cell rate matching unit 3 according to an embodiment of the present invention.

Since the self-synchronizing mixer 211 should be operated only within the payload of the cell, it operates using the SCR CLK signal, and the mixed payload is combined with the cell header through the multiplexer 212 using the MUX SCR as a control signal. The RST SCR is generated when the cell boundary identification and the mixing unit 2 are reset as a mixer reset signal.

4 is a detailed circuit of the self-synchronizing mixer 211 according to an embodiment of the present invention, and the correlation between the input and output of the self-synchronizing mixer 211 is as follows.

This equation can be derived from the series self-synchronizing mixer polynomial.

The parallel HEC encoder 22 of FIG. 2 uses the HEC generation polynomial G (X) = X ⁸ + X ⁴ + X ² +1 recommended by CCITT when the first 4 bytes of the cell are divided by (31 th order polynomial). It is responsible for inserting the remaining 8 bits into the HEC area, which is the fifth byte of the (7th order polynomial) cell.

Looking closely at G (X), it can be seen that it is a generation polynomial of the cyclic code with (n, k) = (127,119). However, since the value we want is (n ', k') = (40, 32), we can see that we generate HEC using shortened cyclic code. The parallel HEC encoder 22 is composed of a HEC submixer 221 designed to facilitate implementation of a high speed protocol and a multiplexer 222 used to insert the HEC into a cell. The signal controlling the HEC submixer 221 is generated in the transmission control section 23 and is shown in FIG.

In order to initialize the HEC submixer 221 for each cell, the HEC ENB signal having a 4-byte clock length synchronized with the Cell CLK is used, and the generated HEC is a cell header through the multiplexer 222 having the MUX HEC as a control signal. Is inserted into the fifth byte in the. The HEC submixer 221 is reset using the HEC RES signal to obtain the HEC of the next cell.

5 is a detailed circuit diagram of the HEC sub-mixer 221 according to an embodiment of the present invention, the correlation between the input and output is as follows.

This equation can be derived from the serial HEC incompatible polynomial.

The parallel HEC decoding unit 24 of FIG. 2 includes a header error control unit 242 and a HEC error control mode for generating syndromes for cell boundary extraction and for determining error patterns (single bit errors and multiple bit errors) in cell headers. Error correction in the HEC state tracking unit 241, the 5-byte shift register 243, and the cell header that tracks the correction mode, the detection mode) and the cell boundary extraction state (tracking state, quasi-synchronous state, and synchronous state). It consists of a correction part 244.

The header error control unit 242 is responsible for generating a syndrome for determining whether an error has occurred in a cell header. The header error control unit 242 obtains a parallel syndrome generation polynomial from a serial syndrome generation polynomial and implements it in byte units in order to facilitate implementation of a high speed protocol. Also, from the generated syndrome, the error occurring in the header is identified as a single bit error or a multi-bit error, and in the case of a single bit error, the error correction unit 244 informs the location where the error occurs and corrects the error. The correlation with the input / output of the error correction unit 244 is as follows.

CUD7 = CUDi7 + E7, CUD6 = i6 + E6,

CUD0 = CUDi0 + E0

The 5-bar art shift register 243 delays the cell delivered to the parallel HEC decode unit 24 for a 5-byte clock to provide a time margin for the header error control unit 242 to correct the error in the cell header.

The header error control unit 242 of the HEC state tracking unit 241 reports the presence or absence of an error in the cell header, and determines the HEC control mode (correction mode, detection mode) and cell boundary extraction state (tracking state, quasi-synchronization state, synchronization state). It provides the ability to track and determine the validity of a cell (delivering or discarding the cell to a higher layer).

The signals controlling the header error control unit 242 and the HEC state tracking unit 241 are signals generated by the reception control unit 26 of FIG. 6.

The SYN_CLK signal is a signal generated by the reception controller 26 itself, and all other signals are generated based on this. The CDSM_CLK signal is a signal corresponding to the first head byte of a cell among the data of CUD ₀ [7: 0].

The SYN_ENB signal is a signal necessary for generating a syndrome in the header error control unit 242, and a DEC-END signal is a signal required for updating the syndrome in order to determine whether there is an error in the header and determine an error pattern in the header error control unit 242.

FIG. 7 illustrates a detailed circuit of the header error controller 242 according to an embodiment of the present invention. The correlation between the input and output of the modulo double addition error 2421 generating a syndrome is as follows. T represents the byte clock period.

By obtaining the syndrome patterns corresponding to all cases where a single bit error occurs within 5 bytes of data, it can be seen that all syndrome patterns are unique. Using this property, if a single bit error occurs among the first byte data exited through the 5-byte shift register 243 of FIG. 2, the corresponding syndrome patterns are all eight types. Therefore, the syndrome pattern matching is performed. Single bit error correction is possible. Since the SYN_ENB signal of FIG. 7 masks all the payload data, it can be seen that when a single bit error occurs in the cell header, the cell header passes through the 5-byte shift register 243 to correct the error. The correlation between the inputs and outputs of the error pattern decoder array 2422 is as follows.

SYND = S ₀ + S ₁ + S ₂ + S ₃ + S ₄ + S ₅ + S ₆ + S ₇

The SYND signal from the error pattern decoder array 2422 is " 0 " when there is no error in the cell header.

The demixing unit 25 of FIG. 2 is inversely mixed with the self-synchronizing inverse mixer 251 which performs parallel inverse inverse-by-byte processing of cells mixed by the polynomial X ⁴³ +1 of a self-synchronizing mixer (SSS). Multiplexer 252 for combining the cell payload and the cell header.

The signal controlling the self-synchronizing inverse 251 is shown in FIG. 6 as being generated at the receiving controller 26.

The self-synchronizing demixer 251 is used to extract and demix the DSCR-CLK signal since it should be operated only within the payload of the cell. The demixed payload is combined with the cell header through the multiplexer 252 using the MUX-DSCR as a control signal. The combined cell data flow, CUD ₀ [7: 0], is passed to the cell rate matcher 3.

8 is a detailed circuit of the self-synchronizing inverse mixer 251 according to an embodiment of the present invention. This equation can be derived from the series self-synchronizing inverse mixer 251.

r ₁ (t + 1) = r _1-8 (t) = 8,9, ..... 42, t: byte clock period

The HEC state tracking unit 241 of FIG. 9 receives the presence or absence of an error in the cell header from the header error control unit 242, and the HEC control mode (correction mode, detection mode) and cell boundary extraction state (tracking state, quasi-synchronization). Delta counters of the HEC state tracker 2411 and the ALPHA counter 2412 that provide the ability to determine the validity of a cell (delivering or discarding the cell to a higher layer) by tracking state and sync. 2413).

The alpha counter 2412 is a counter for counting the number of cells in error in the header in a synchronous state, and is incremented only when there is an error in the cell header continuously, and resets if there is no error in the cell header at least once.

The delta counter 2413 is a counter that counts the number of cells without errors in the header in the quasi-synchronized state. If an error occurs in the cell header even once, the counter is reset and the HEC state tracker 2411 operates in the tracking state. do. Details accept the behavior of the CCITT Recommendations.

The instruction register 271 and status register 272 shown in FIG. 10 are configured to be 8 bits wide in order to provide a function for performing layer management and maintenance including a loopback test in the physical layer management unit. If the physical layer management unit configures the cell boundary identification and hybridization functions or performs the loopback test, such a function can be performed by appropriately setting the command register 271 in the cell boundary identification and hybridization apparatus. The apparatus 2 includes a cell boundary identification state (tracking state, quasi-synchronization state, synchronization state), HEC control mode (modification mode, detection mode), whether or not an error occurs in the cell header and the type of error (single bit error, multiple bit) Error) is reported to the physical layer management unit as the status register 272, so that the physical layer management unit can appropriately use it.

11 is a detailed block diagram of the transmission control unit 23 according to an embodiment of the present invention. CELL-Clk is transmitted through the 4-byte shift register 231, and Q [Q] which is an output signal of the shift registers 231 is shown in FIG. 4: 1], the transmitter control signal generator 232 generates the necessary signals.

12 is a detailed block diagram of the reception control unit 26 according to an embodiment of the present invention, and generates necessary signals by receiving the 53/54 binary counter 261 and the output signal Q [5: 0]. And a receiver control signal generator 262. The reception control unit 26 provides a function of controlling the cell boundary extraction unit by tracking the HEC control mode and the cell boundary extraction state from the HEC state tracking unit 24. In other words, in the cell tracking state, an arbitrary 54-byte cell is constructed from the data transmitted through the physical medium connection unit 1, and an error in the cell header is checked. After constructing the virtual cell again after the next 1 byte, the cell's header is periodically checked to generate an synchronous clock. The 53/54 binary counter 261 receives the PS [7: 0] from the HEC state tracking unit 241 and operates as a 54 binary counter when the current cell division is in the tracking state. It works. Using this method, we can see that the cell can be synchronized within a maximum of 52 attempts. In the quasi-synchronous state or the synchronous state, only a fixed 53-byte clock length cell synchronization clock exists, and various control signals are generated based on this reference.

Accordingly, the present invention, which is configured and operated as described above, is used to process ATM cell boundary identification and intermingling functions in units of bytes among physical layer functions supporting the ATM protocol. By using the header error decoder technique rather than the up method, the hardware burden is reduced, and all functions are processed in units of bytes, and thus the function can be implemented at the TTL level. In addition, there is an effect of acquiring the core technology of the ATM physical layer protocol suitable for high-speed information transmission, and in the future, this functional device can be utilized for ATM network termination devices and ATM terminal matching devices, which are various devices constituting the broadband integrated information communication network.

Claims (5)

A cell boundary identification and blending apparatus in an ATM protocol physical layer, comprising: a mixing unit 21 for mixing a 48-byte payload in bytes in a 53-byte cell transmitted from a cell rate matching unit 3, and a 5-byte Parallel HEC encoding means 22 for receiving the first 4 bytes of the cell header in byte units to generate a HEC (Header Error Control), and inserting the same into the fifth byte, the mixing means 21 and the parallel HEC encoding means ( A transmitter having a transmission control means 23 for controlling 22; Parallel HEC decoding means 24 for controlling cell boundary extraction and errors in cell headers from the byte unit data transmitted from the physical medium connection 1, and the original cell payload in the mixed 48-byte payload. A receiving unit including a decoupling means 25 for restoring, a reception control means 26 for controlling the parallel HEC decoding means 24, and a decoupling means 25, a reception control means 23, and a receiving portion; And a status register (272) coupled to the control means (26). 2. The self-synchronizing method of claim 1, wherein the mixing means 21 processes the polynomial X ⁴³ +1 of the self-synchronizing sclerber (SSS) recommended by the CCITT for SDH-based transmission. And a multiplexer 212 for receiving a multiplexer 211 and an output of the self-synchronized mixer 211 and an input of the self-synchronized mixer 211 as inputs and multiplexing them. (ATM) Cell Boundary Identification and Admixture. The HEC encoder according to claim 1, wherein the parallel HEC encoding means 22 receives an output of the multiplexer 212 in the mixing means 21 and is responsible for a parallel HEC encoding function to facilitate implementation of a high speed protocol. And a multiplexer 222 for multiplexing the input of the HEC encoder 221 and the output of the HEC encoder 221 to insert the HEC into the cell. ) Cell boundary identification and admixture. The method of claim 1, wherein the parallel HEC decoding means (24) comprises: a header error control unit (242) for generating syndromes for cell boundary extraction and for determining error patterns (single bit errors and multiple bit errors) in the cell header; And a HEC state tracking unit 241 for tracking the HEC error control mode (correction mode, detection mode) and the cell boundary extraction state (tracking state, quasi-synchronous state, synchronization state), and delaying the input cell for 5 byte clocks. A 5-byte shift register 243 for providing a time margin for correcting an error in the header after the header error control unit 242 determines whether there is an error in the cell header, and the header error control unit 242 and the 5 bytes. And an error correction unit (244) connected to the shift register (243) to correct errors in the cell headers. The apparatus of claim 1, wherein the demixing means (25) is configured to perform parallel inverse of the cells mixed by the multidirectional X ⁴³ +1 of the self-synchronizing scrubber (SSS) 211 of the transmitter. A byte-processing ATM cell boundary identification and blending apparatus having a self-synchronizing demultiplexer 251 for mixing and a multiplexer 252 for multiplexing to combine the demixed cell payload and the cell header. .