JP2001057559A - Multi-link communication device and its method in atm - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-link communication device and its method in an ATM that transmits synchronization information between multi-links without giving effect on a communication band used by a user. SOLUTION: First cell reception circuit 40 to n-th cell reception circuit 42 receive an ATM cell with a synchronization pattern inserted thereto while being deviated among links. First cell synchronization circuit 50 to n-th cell synchronization circuit 52 detect an ATM cell with a synchronization pattern inserted thereto, ATM cells with a synchronization pattern inserted to them are arranged and outputted according to an instruction from a 2nd reception timing generating circuit 71.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchronous Transfer Mode) for transmitting synchronization information between multiple links without reducing a communication band available to a user.
And a multi-link communication device and method.

[0002]

2. Description of the Related Art Today, ATM-based communications have become widespread in the social infrastructure, and are provided by NTT megalink networks provided by NTT.
Services and the like are set at a lower price than ordinary dedicated line services.

On the other hand, a user who uses a dedicated line service including an ATM megalink service contracts a dial-up line such as INS64 or INS1500 for the purpose of backup in the event of a failure, and provides a communication route even in the event of a failure. Is secured.

[0004] However, when communication is performed using a plurality of B channels in the INS 64 or INS 1500 (multi-link communication), the transmitted plurality of B channels do not always arrive with the same time delay. In some cases, a high-speed leased line cannot be contracted due to circumstances, and a plurality of low-speed leased lines may be substituted for the leased line. In this case, the same problem as a dial-up line occurs.

[0005] In the Internet and the like, where the traffic has been explosively increasing recently, in order to solve the above problem, P
PP-MP (PPP Multilink Protocol. RFC
Specified in 1717 and RFC 1990. ) And so on. In ATM communication, IMA (AT
Inverse multiplexing in M. ATMF
Specified by orum. ) And other technologies.

[0006]

SUMMARY OF THE INVENTION However, ATM
The IMA technology in communication has the following problems.

A first problem is that a special ATM cell (ICP cell: IMA control protocol cell) is inserted at regular intervals to synchronize links. By inserting a special ATM cell, the bandwidth available to the user is reduced correspondingly.

The second problem is that a special ATM cell (IC
Since the content of “P cell” is set not in the header but in the payload, the processing tends to be complicated.

Therefore, the present invention solves the above-mentioned conventional problems without affecting the communication band available to the user.
It is an object of the present invention to provide a multi-link communication device and method in an ATM for transmitting synchronization information between multi-links.

[0010]

In order to solve the above-mentioned problems, the present invention comprises a transmitting device and a receiving device for performing multi-link communication by the ATM system, wherein the transmitting device comprises a plurality of transmitting devices for transmitting data. In correspondence with links 1 to n (n is a natural number of 2 or more), n cell transmission circuits for transmitting ATM cells, and n × m (m is a natural number of 2 or more) consecutive ATM cells, m cells are distributed to n cell transmission circuits, and at the time of distribution, m consecutive ATs are distributed.
A virtual path identifier (VPI) / virtual path identifier (VCI) in the cell header of the M cell at the synchronous position.
Channel Identifier) has a synchronization pattern insertion / distribution circuit that inserts a predetermined synchronization pattern into unused bit areas in the area, and the receiving apparatus receives a signal corresponding to the links 1 to n. N cell receiving circuits for establishing cell synchronization of ATM cells, and corresponding to the n cell receiving circuits, detecting an ATM cell into which a synchronization pattern to be received for every m cells is inserted, and synchronizing with a timing signal. And n synchronization circuits for sequentially outputting each ATM cell;
Each of the ATM cells output in this order is rearranged in the original order and multiplexed to form continuous n × m ATM cells. When multiplexing, the ATM cell into which the synchronization pattern has been inserted is replaced with the synchronization pattern. Delete sync pattern
And a multiplexing circuit.

With the above configuration, synchronization between links is achieved by using an unused bit area in the VPI / VCI area in the ATM cell header.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration of a transmission circuit according to the present invention. The transmitting device 1 receives the continuous AT from the cell transmitting circuit 2.
A synchronization pattern insertion circuit 10 for inserting a predetermined synchronization pattern into an M cell, into an unused bit area in a VPI / VCI area in an ATM cell header.
have. The continuous ATM cells received from the cell transmission circuit 2 received by the synchronization pattern insertion circuit 10 include not only valid cells but also empty cells (idle cells) inserted and extracted for speed matching in the physical layer. I have. Also each A
The VPI / VCI area in the header of the TM cell is a total of 24 bits (at the time of UNI) or 28 bits (at the time of NNI), but usually does not use all the bits. The synchronization pattern insertion circuit 10 unconditionally inserts a predetermined synchronization pattern into an unused area of the VPI / VCI area in the ATM cell header.

The header portion of each ATM cell is composed of a 5-byte area, and the fifth byte is a header error control (HEC).
Allocated to bytes. HEC has ATM cells
The cyclic redundancy code (CRC) calculation results from the first byte to the fourth byte of the header are inserted, and the receiving side checks whether there is an error in the ATM cell header based on the same calculation method as the transmitting side. to decide.

The result calculated by the cell transmission circuit 2 is inserted into the HEC portion of the continuous ATM cells received by the synchronization pattern insertion circuit 10. HEC calculation circuit 11
Is a circuit for inserting a new calculation result into the HEC area by inserting a synchronization pattern into the header by the synchronization pattern insertion circuit 10. The delay circuit 12 delays continuous ATM cells from the cell transmission circuit 2 by the same time as the time required for processing by the synchronization pattern insertion circuit 10 and the HEC calculation circuit 11, and the selection circuit 13 includes a cell transmission circuit An ATM cell in which a synchronization pattern is inserted into each ATM cell transmitted from No. 2 and an ATM cell in which a synchronization pattern is not inserted arrive at the same time.

In the selection circuit 13, an instruction of the selection signal generated by the first transmission timing generation circuit 20 is used to output the HE signal.
ATM with synchronization pattern inserted from C calculation circuit 11
Either a cell or an ATM cell into which the synchronization pattern from the delay circuit 12 is not inserted is selected and sent to the separation circuit 14. When transmitting continuous ATM cells from the cell transmission circuit 2 using the links 1 to n, the selection signal generated by the first transmission timing generation circuit 20 includes n ATM cells having the synchronization pattern inserted therein. This is a selection signal that selects and then selects n × (m−1) ATM cells into which no synchronization pattern is inserted, and thereafter repeats this. M is an arbitrary value determined in advance between the transmitting device 1 and the receiving device 3.

The separation circuit 14 converts continuous ATM cells received from the selection circuit 13 from the first cell transmission circuit 30 to the n-th cell transmission circuit in accordance with a selection signal from the second transmission timing generation circuit 21. 32 in order.
When transmitting the continuous ATM cells from the cell transmission circuit 2 using the data transmission links 1 to n, the selection signal generated by the second transmission timing generation circuit 21 is selected by the selection circuit 13. The first cell among the n consecutive ATM cells into which the synchronization pattern has been inserted is sent to the first cell transmission circuit 30, and then the second cell transmission circuit 31 sends the n-th cell to the nth ATM cell.
Are sequentially transmitted to the cell transmission circuit 32, and thereafter are repeated selection signals.

Next, FIG. 2 shows a configuration of a receiving circuit according to the present invention. The receiving device 3 includes a first cell receiving circuit 40 to an n-th cell receiving circuit 42 for establishing cell synchronization of continuous ATM cells received from the links 1 to n. In the first synchronization circuit 50 to the n-th synchronization circuit 52, the first cell reception circuit 40 to the n-th cell reception circuit 42
Receives the continuous ATM cells in which the ATM cell synchronization has been established, detects the ATM cells into which the synchronization pattern has been inserted, which appear for each of the m ATM cells, and generates the synchronization signal indicated by the second reception timing generation circuit 71. Then, the ATM cell with the synchronization pattern inserted is sent to the multiplexing circuit 60 in order from the ATM cell.

The multiplexing circuit 60 selects and multiplexes the ATM cells received from the first synchronization circuit 50 to the n-th synchronization circuit 52 in order according to the selection signal instructed from the second reception timing generation circuit 71. , Continuous ATM cells. The synchronization pattern deletion circuit 61 unconditionally deletes a predetermined synchronization pattern from an unused area in the VPI / VCI area in the ATM cell header. The HEC calculation circuit 62 calculates the A
The CRC operation result is inserted into the HEC area based on the TM cell header. The delay circuit 63 is a circuit for delaying the continuous ATM cells from the multiplexing circuit 60 by the same time as the time required for processing by the synchronization pattern deleting circuit 61 and the HEC calculating circuit 62. An ATM cell from which the synchronization pattern has been deleted from each transmitted ATM cell and an ATM cell from which the synchronization pattern has not been deleted arrive at the same time.

The selection circuit 64 is configured to select the ATM cell from which the synchronization pattern from the HEC calculation circuit 62 has been deleted by the selection signal instructed by the first reception timing generation circuit 70,
ATM where the synchronization pattern from the delay circuit 63 is not deleted
One of the cells is selected and sent to the cell receiving circuit 4.

Next, the operation of the transmitting apparatus and the receiving apparatus according to the present invention will be described with reference to FIGS.

FIG. 3 shows a state in which a synchronization pattern is inserted into continuous ATM cells output from the cell transmission circuit 2 and transmitted from the first cell transmission circuit 30 to the n-th cell transmission circuit 32 in order. FIG. Consecutive ATM cells output from the cell transmission circuit 2 are referred to by repetition numbers 1-1 to mn for convenience.

The transmission circuit block 15 is constituted by the circuit described in FIG. As described above, the cells are sequentially transmitted one by one from the first cell transmission circuit 30 to the n-th cell transmission circuit 32, and a synchronization pattern is inserted in the first cell of the m blocks. The ATM cells inserted with the synchronization pattern transmitted to the links 1 to n all appear at the same time on each link.

FIG. 4 shows that the ATM cell transmitted in FIG.
FIG. 9 is an explanatory diagram showing a state where the receiving device has reached a receiving device via an external network. Each link has a different delay time,
The ATM cell into which the synchronization pattern has been inserted is received with a shift between the links, for example, as shown in the figure. ATM received
If cells are multiplexed as they are, communication cannot be established because continuous ATM cells from the cell transmission circuit 2 in FIG. 3 cannot be restored.

The first cell synchronization circuit 50 to the n-th cell synchronization circuit 52 shown in FIG. 4 detect the ATM cell into which the synchronization pattern is inserted, and change the synchronization pattern according to the instruction from the second reception timing generation circuit 71. The inserted ATM cells are output together.

FIG. 5 is an explanatory diagram showing a state in which the synchronization pattern of the ATM cells output from the respective cell synchronization circuits is deleted, rearranged again in order, and restored to the original signal.

In this way, the order of the ATM cells received via the external network is correctly restored when received by the cell receiving circuit 4.

Next, another embodiment of the present invention will be described.

As described in the above embodiment, A
The header part of the TM cell has an HEC area. The receiving side uses this HEC information to transmit the transmitted ATM.
Even if a 1-bit error occurs in the header portion of the cell, it can be corrected. By utilizing the redundancy of the header portion, it is possible to notify synchronization information between multiple links. In other words, rather than inserting a synchronization pattern into an unused area of the VPI / VCI, the transmitting side inverts one bit of the header portion of the ATM cell at regular intervals and detects a correctable one-bit error on the receiving side. By doing so, synchronization information is transmitted.

The quality of recent transmission lines is very good, and the probability of occurrence of bit errors in the transmission lines is low. With the above method, synchronization between multiple links is established without reducing the VPI / VCI area.

As described above, the present invention achieves multi-link in ATM by synchronizing links using unused bit areas in the VPI / VCI area in the ATM cell header. It realizes communication.

On the transmitting side, n consecutive ATs in which a synchronization pattern predetermined by the synchronization pattern insertion circuit 10 is inserted.
The M cells are sequentially transmitted to the links 1 to n by the first cell transmission circuit 30 to the n-th cell transmission circuit 32 by the selection circuit 13 and the separation circuit 14. Thereafter, the selection circuit 13 and the separation circuit 14 receive the n × (m−1) from the delay circuit 12.
Number of consecutive ATM cells are transmitted to the first cell transmission circuit 30 to
In the n-th cell transmission circuit 32, transmission is sequentially performed to the links 1 to n, and thereafter, this is repeated.

On the receiving side, the first cell receiving circuit 40 to the n-th cell receiving circuit 42 receive signals A received from the links 1 to n.
Establish cell synchronization of TM cells. First synchronous circuit 50-
The n-th synchronization circuit 52 detects the ATM cells into which the synchronization pattern to be received is inserted every m cells, and sequentially transmits the ATM cells to the multiplexing circuit 60 based on the timing from the second reception timing generation circuit 70. The selection circuit 64 selects at regular intervals n continuous ATM cells from which the synchronization pattern has been deleted by the synchronization pattern deletion circuit 61, and
Send to

As described above, the transmitting device 1 and the receiving device 3
With this configuration, continuous ATM cells transmitted by the cell transmission circuit 2 can be received by the cell reception circuit 4 without changing the order.

[0035]

As described above, the present invention does not transmit a special ATM cell when synchronizing between multiple links, but does not use the ATM cell header in a normal usage. In the upper bit area of VPI / VCI,
Since the synchronization pattern information is inserted, the synchronization information between multiple links can be transmitted without affecting the communication band available to the user. For this reason, if the user performs n multi-link communications, the bandwidth per link n
Double bandwidth can be secured.

The synchronization information between the multi-links is A
Since the synchronization information is set in the header of the TM cell, the synchronization information can be found by a relatively simple procedure. Therefore, when synchronizing between multiple links, a complicated procedure for interpreting the payload of the ATM cell is required. do not need.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a transmission circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a receiving circuit according to the present invention.

FIG. 3 is an explanatory diagram illustrating a state of a transmission signal from a transmission device.

FIG. 4 is an explanatory diagram showing a state of a signal reaching a receiving device.

FIG. 5 is an explanatory diagram showing a state where the original signal is restored by the receiving device.

[Explanation of symbols]

 1 transmitting device 3 receiving device

Claims (6)

[Claims] The present invention comprises a transmitting device and a receiving device for performing multi-link communication according to an ATM system, wherein the transmitting device comprises a plurality of links 1 to n for transmitting data.
(N is a natural number of 2 or more) corresponding to n cell transmission circuits for transmitting ATM cells, and n × m (m is a natural number of 2 or more) consecutive ATM cells M is distributed to the transmission circuit at a time, and at the time of distribution, the VPI / VC in the cell header at the synchronous position of each of the m consecutive ATM cells.
A synchronization pattern insertion / distribution circuit for inserting a predetermined synchronization pattern into an unused bit area of the I area, wherein the receiving device receives the ATM cells corresponding to the links 1 to n; N cell receiving circuits for establishing cell synchronization of the above, and corresponding to these n cell receiving circuits, detecting ATM cells in which a synchronization pattern to be received is inserted every m cells, and synchronizing with a timing signal. , N synchronization circuits for sequentially outputting each ATM cell, and multiplexing by rearranging the ATM cells output in this order in the original order to form n × m continuous ATM cells. When the synchronization pattern is deleted, the synchronization pattern is deleted from the ATM cell into which the synchronization pattern is inserted.
A multi-link communication device in an ATM, comprising a multiplex circuit. 2. A transmitting apparatus and a receiving apparatus for performing multi-link communication according to an ATM system, wherein the transmitting apparatus does not use a VPI / VCI area in a cell header of a continuous ATM cell. A synchronization pattern insertion circuit for inserting a predetermined synchronization pattern into a bit area; and n number of links for transmitting ATM cells corresponding to a plurality of links 1 to n (n is a natural number of 2 or more) for transmitting data. After sequentially outputting the n consecutive ATM cells with the cell transmission circuit and the synchronization pattern inserted thereto to the n cell transmission circuits, n × (m−1) (m is 2) cells without the synchronization pattern inserted A selection / separation circuit for sequentially outputting ATM cells having the above (natural numbers) to the n cell transmission circuits, wherein the receiving apparatus receives the received AT corresponding to the links 1 to n. N cell receiving circuits for establishing cell synchronization of cells, and corresponding to the n cell receiving circuits, detecting ATM cells into which a synchronization pattern to be received is inserted every m cells, and synchronizing with a timing signal. And n multiplexing circuits for sequentially outputting the ATM cells, a multiplexing circuit for multiplexing the ATM cells output in this order and outputting them as continuous ATM cells, and an ATM cell having a synchronization pattern inserted therein. And the AT from which the synchronization pattern has been deleted.
M cells and ATM cells from which the synchronization pattern is not deleted are selected, rearranged in the original order, and successive n × m ATs
A multi-link communication device in an ATM, comprising: a synchronization pattern deletion / selection circuit for outputting as an M cell. 3. A transmitting apparatus and a receiving apparatus for performing multi-link communication according to an ATM system, wherein the transmitting apparatus comprises a plurality of links 1 to n for transmitting data.
(N is a natural number of 2 or more) corresponding to n cell transmission circuits for transmitting ATM cells, and n × m (m is a natural number of 2 or more) consecutive ATM cells A receiver for distributing m pieces of data to the transmitting circuit, and for distributing the m pieces of ATM cells, a bit inverting / distributing circuit for inverting one bit of a cell header at a position synchronized with each of m consecutive ATM cells; Corresponding to the links 1 to n, n cell receiving circuits for establishing cell synchronization of the received ATM cells; and ATM cells for receiving m every m cells corresponding to the n cell receiving circuits. And n synchronous circuits for sequentially outputting the ATM cells in synchronism with the timing signal based on the detected position. Reorder in order and multiplex and continue × together with the m ATM cell, at the time of multiplexing, a multi-link communication system in an ATM, characterized in that it comprises a correction-multiplexing circuit for correcting bit inversion of the detected cell header. 4. A communication apparatus for performing multi-link communication according to an ATM system, comprising: a transmitting apparatus for transmitting a plurality of consecutive n × m (m, n is a natural number of 2 or more) ATM cells to a plurality of links for transmitting data; 1
.. N, and at the time of distribution, unused bit areas of the VPI / VCI area in the cell header at the synchronous position of the m consecutive ATM cells. , A predetermined synchronization pattern is inserted into the receiving device, and the receiving device receives the received A according to the links 1 to n.
The cell synchronization of the TM cells is established. From these ATM cells, ATM cells into which a synchronization pattern to be received is inserted for every m cells are detected, and each ATM cell is synchronized with a timing signal. The cells are rearranged in the original order and multiplexed to form continuous n × m ATM cells, and when multiplexing, the synchronization pattern is deleted from the ATM cell in which the synchronization pattern is inserted. Multi-link communication method in ATM. 5. A communication device for performing multi-link communication according to the ATM system, wherein a transmitting device transmits an unused bit region of a VPI / VCI region in a cell header of n consecutive ATM cells. , A predetermined synchronization pattern is inserted, and n consecutive ATs into which these synchronization patterns are inserted
M cells are sequentially output to a plurality of links 1 to n (n is a natural number of 2 or more) for transmitting data, and then n × (m−1) (m is a natural number of 2 or more) without inserting a synchronization pattern ) Are sequentially output to the links 1 to n.
The cell synchronization of the TM cells is established. From these ATM cells, ATM cells into which a synchronization pattern to be received is inserted for every m cells are detected, and each ATM cell is synchronized with a timing signal. A cell is multiplexed and successive A
The ATM cell in which the synchronization pattern is deleted from the ATM cell into which the synchronization pattern is inserted, and the ATM cell in which the synchronization pattern is deleted.
M cells and ATM cells from which the synchronization pattern is not deleted are selected, rearranged in the original order, and successive n × m ATs
A multi-link communication method in an ATM, comprising outputting as an M cell. 6. A communication apparatus for performing multi-link communication according to an ATM system, wherein a transmitting apparatus transmits a plurality of consecutive n × m ATM cells (m and n are natural numbers of 2 or more) to a plurality of links for transmitting data. 1
M, and when distributing, the receiver inverts one bit of the cell header at the synchronous position of each of the m consecutive ATM cells, and A corresponding to the received A
Establish cell synchronization of TM cells, detect errors in cell headers of ATM cells received every m cells from these ATM cells, and synchronize each ATM cell with a timing signal based on the detected position. The ATM cells synchronized in the above are rearranged in the original order and multiplexed,
A multi-link communication method in an ATM, comprising the step of correcting the detected bit inversion of the cell header when multiplexing a plurality of consecutive ATM cells.