KR960001949B1 - General purpose neural network circuit board adaptable to an - Google Patents

Abstract

a first buffer for supplying a clock signal to 36 parallel processors without time delay; a second buffer for producing an input/output ready signal of an AT-bus; a fourth buffer for connecting the AT-bus and a process board; a third buffer for sending an output signal from the fourth buffer to a decoder; a fifth buffer for outputting a record and read control signal of a memory; a decoder for decoding an address and data value from the AT-bus; a first selector for producing a signal which selects a DNP chip; a fourth selector for selecting a run or reset signal; a fifth selector for producing a RAM operating signal; a second selector for outputting a memory select signal to the parallel processor; a third selector for outputting a buffer enable signal to the parallel processor; a first communication unit for receiving a flag state of data input/output state check value of the DNP chip through the fourth buffer and for allowing a PC to read the flag state; a third communication unit for allowing an IBM-PC to read a set value of the flag state through the fourth buffer; and a second communication unit for allowing the IBM-PC to read or write data at an input/output port through the fourth buffer.

Description

General purpose neural network board for connection with IBM-PC

1 is a configuration of the neural network board and the overall system configuration.

2 is a complete array of parallel processors.

3 is a schematic diagram of one PE in a parallel processor.

4 is a top level configuration of a board according to the present invention.

5 is a configuration diagram of a memory address map.

6 is a configuration diagram of another display example according to FIG.

* Explanation of symbols for main parts of the drawings

1: neural network board 2: parallel processor

3: I / O interface 4: IBM-PC

5: PE (Processing Element): DNP (Digital Neural Processor)

6: RAM 7: Buffer

8: base module of one of the parallel processors

The present invention relates to a general purpose neural net board that can be used in connection with a personal computer (IBM-PC).

This board is called E-MIND (ETRI-Machine Imitating Neuro Dynamics) board.

E-MIND board is designed for high speed operation using parallelism, and there are 36 PE (processing elements) corresponding to CPU of general computer.

The PE is composed of a digital neural processor (DNP), and the DNP is an 8-bit multiple-instruction multiple-data (MIMD) processor designed by the ETRI for simulation of neural network models. .

Details of the DNP structure are described in a patent application (Application No. 90-21852, December 26, 1990).

The E-MIND board connects to the AT bus of the IBM-PC and controls the board's operation by reading and writing data to a free memory space on the PC. The result of the controlled operation can thus be seen on the monitor of the PC.

1 shows the overall system configuration with the configuration of a general E-MIND board.

The neural network board 1 is composed of two parts, a parallel processor 2 consisting of 36 basic modules (PAS) and an I / O interface 3 for data exchange.

And the whole system is connected to the IBM-PC (4).

In other words, the operation of the entire system carries the addresses and data required on the AT-bus (or XT-bus) of the IBM-PC 4.

Then, the data required by the parallel processor is stored in the external memory, and the program of the neural chip (DNP) is downloaded to the neural chip.

The 36 neural chips in the parallel processor can then download their own programs (negative chips to the MIMD type processor) using the connection circuitry from the IBM-PC (4).

2 shows the arrangement and connection status of the PASF parts.

In the PASF part, as shown in FIG. 2, one PE is connected to four neighboring PEs in a two-dimensional plane, and communication between the PEs occurs with one of the four PEs adjacent by a program.

PEs 11, 17, 23, 29, and 35 at the top right are connected to PEs 0, 1, 2, 3, and 4 at the bottom, respectively, to form a feedback loop.

This connection allows the data flow to be unidirectional with the output connected to the input, which is effective when used as a classifier using neural network models.

The parallel processor (PASF) structure is described in patent application (application no. 90-21850, December 26, 1990).

3 shows a configuration of one basic module of a parallel processor (PASF). The configuration consists of one PE (5: DNP), a data RAM (6) and two buffers (7a, 7b).

It is PASF that these 36 modules are connected in a mesh form with feedback and arranged for efficient communication by the address bus and data bus.

Thus, although the MIMD type parallel processor 2 was completed, there was no efficient interface circuit for the connection between the parallel processor 2 and the IBM-PC 4.

Accordingly, an object of the present invention is to provide a general-purpose neural network board having an interface circuit capable of efficiently executing an electrical connection for signal transmission between a MIMD type parallel processor and an IBM-PC.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention for achieving the above object will be described in detail.

4 is a configuration diagram of the top level of the entire neural network board of the present invention.

In FIG. 4, the same reference numerals are used for components that perform the same functions for the components shown in FIGS. 1 to 3. In FIG. 4, the PASF corresponding to the processor corresponds to the reference number 2, and the remaining part corresponds to the I / O interface circuit.

Referring to FIG. 4, the configuration of the neural network board 1, which includes an interface device for controlling the performance of data transmission between the IBM-PC 4 and the MIMD type parallel processor 2, includes a clock ( The first buffer 11 which raises the CLK signal and distributes it to 36 parallel processors 2 without time delay, and the I / O wait signal (IO-RDY signal) which enters the IBM-PC 4 (AT-Bus protocol collection Memory write / read signals (MEMW, MEMR) and data signals by connecting the second buffer 12 to the second buffer 12, the AT-bus (or XT-bus) slot of the IBM-PC 4, and the processor board. (SD0-SD7), an address signal (SA0-SA23), a drive reset (DRV-RESET) is exchanged with the IBM-PC (4) and the fourth buffer 14 and output from the fourth buffer (14) Recording of the third buffer 13, which is a power buffer for raising the signal to the decoder 21, and the memory (RAM 6 in FIG. 3) output from the fourth buffer 14 and in the parallel processor 2 And A fifth buffer 15 for outputting the read control signal and a decoder for decoding the address and data values from the AT-bus (or XT-bus) of the IBM-PC 4 through the fourth buffer 14 ( 21 and a first selector 43 for generating a signal for selecting a DNP (Digiatal Neural Processor) chip in the parallel processor 2 by a signal decoded by the decoder 21 (using a DNS select register code). And a fourth selector 41 which receives a signal decoded by the decoder 21 and selects a RUN or reset signal for operating the parallel processor 2, and the decoder 21 A fifth selector 42 which receives the decoded signal and generates a RAM operation signal of the parallel processor 2, a RUN signal state selected by the fourth selector 41, and the fifth selector The memory (RAM) operation signal selected in (42) is combined (using the off-chip RAM code) so that the memory selection signal (RAM_CS: this signal is incorrect). Receiving a RAM operation signal selected by the second selector 44 and the fifth selector 42 for outputting a memory (creating a selection signal of '6' in FIG. 3) to the parallel processor 2; A third selector 45 for outputting a buffer enable signal BUF_EN to the parallel processor 2 using the DNP chip select signal DNP_CS selected by the first selector 43, and the parallel processor 2. ) And the data input / output status check (IRS, ORS) codes (addresses and data values from the IBM-PC 4) are decoded by the decoder 21 when the IBM-PC 4 is on-line. The first communication unit 31, the parallel processor 2, and the IBM- receive the flag state of the data input / output state check value of the DNP through the fourth buffer 14 and allow the IBM-PC 4 to read it. When the PC 4 is in the on-line state, the data input / output status check (IRS, ORS) codes (addresses and data values from the IBM-PC 4) are decoded by the decoder 21. If the flag state of the flag state value of the data input / output state check value of the DNP is set according to the coded result, the IBM-PC 4 reads the set value from the parallel processor through the fourth buffer 14. When the third communication unit 33, the parallel processor 2 and the IBM-PC 4 are in the on-line state, the data in the input / output port of the DNP is determined according to the result of the decoding of the data input / output code by the decoder 21. The second communication unit 32 to the IBM-PC (4) to read or write through the fourth buffer (14).

The interface device is housed on the neural network board 1 and is integrally formed.

The operation of the I / O interface circuit of the E-MIND board can be divided into two parts according to the state in which the E-MIND board 1 operates and does not operate.

First, in the state where the E-MIND board 1 does not operate, the decoder 21 and the selectors 41 to 45 are used for the program inside the DNP among the basic modules of the parallel processor (PASF) 2. Up / down loading programs and data required for RAM and external local memory respectively. In the state where the E-MIND board 1 operates, the communication units 31 to 33 use the communication units 31 to 33 to communicate data with the PEs 0, 1, 2, 3, 4, 5 at the bottom of the board, and the IBM-PC. It is possible to send and receive, and the communication status thereof can be viewed on the IBM-PC 4 through the communication units 31 to 33.

Through the communication with the PEs at the bottom to determine whether the operation of the parallel processor (2) is completed.

The signal input to the E-MIND board 1 in FIG. 1 uses the same names as the signals provided on the bus of the IBM-PC 4.

In the above, the third buffer 13 and the fourth buffer 14 connect the bus of the IBM-PC 4 with the E-MIND board 1, and the first buffer 11 and the fifth buffer 15. ) Drives 36 PEs.

The remaining second buffer 12 generates an input / output wait signal (IO-RDY signal) among the bus signals of the IBM-PC 4.

The decoder 21 decodes the address output from the IBM-PC 4 via the fourth buffer 14 and sends a signal to the first to fifth selectors 41 to 45. The decoders 21 directly control the first to third communication units 31 to 33.

At this time, the first to third communication units 31 to 33 are the lowermost 0, 1, 2, 3, 4, of the IBM-PC 4 and the parallel processor 2 while the E-MIND board 1 is operating. It sends and receives data with PEs 5 and puts a flag register to check the operation status regarding communication between the lowest PEs and IBM-PC (4).

This confirmation of the operation state is to see the value of the pin related to communication in the DNP chip.

The first to fifth selectors 41 to 45 generate the control signals necessary for the respective modules of the RAM part by using the signal from the decoder 21. Among the selectors 41 to 45, the third selector 45 uses a tri-state buffer for selection of data that is not needed when the parallel processor 2 is operated or not. .

The fourth selector 41 generates an operation signal of the neural network board 1 by outputting an ID-RUN signal by the control signal decoded through the decoder 21.

The control signal from these selectors 41 to 45 controls the processor as follows.

The RAMs select and use RAM as a method of writing data to the address assigned directly by the IBM-PC (4).

In other words, in order to write data to RAM, an empty memory space is required in the IBM-PC 4 corresponding to 256 bytes x 32 PE.

Here, six PEs are selected at a time in the horizontal direction, and the value of the horizontal to be selected is loaded on the data bus of the IBM-PC 4.

The value loaded on the data bus of the IBM-PC 4 is stored in a register to maintain the selected state of the PE until a change occurs.

The overall operation of the general-purpose neural network board including the interface circuit as described above is as follows.

The data and address values used for the interface circuits come from the XT-bus (or AT-bus) of the IBM-PC (4).

The interface circuit operates using the data and the address value. When the interface circuit operates normally, the parallel processor operates normally.

Therefore, the signal from the IBM-PC 4 first passes through the decoder 21 to select a control signal required by the user, such as the selectors 41 to 45, the buffers 11 to 15, and the communication units 31 to 31. 33) can be generated.

By using the control signal generated here, the user can control the entire system.

A part of the control signal generated above enters the first selector 43 to generate a signal capable of selecting 36 parallel processors 2.

This signal is then used for some of the select signals from the base module in the parallel processor.

The signal to be controlled here is selected only if the 36 parallel processors need to be selected independently.

That is, signals for selecting a neural chip in the basic processor module (since the chip operates normally when the chip is selected), signals for selecting a memory, and enable signals for operating a buffer.

These signals can be used to transfer the programs and data needed for a particular chip (otherwise, the MIMD characteristics cannot be used).

These signals are the smallest possible signals for this purpose (all these signals can be generated independently, which makes it difficult to control because they are parallel systems, and too many signals flow on the board, making boards difficult).

The other signals are grouped together and selected simultaneously.

As a result, the signals that are simultaneously selected as a whole are decoded and passed through the buffers to 36 parallel processors simultaneously.

As such, the buffer is simply a power buffer that a single TTL can't use to transmit signals to multiple chips at the same time.

Data and addresses coming into the parallel processor from the IBM-PC 4 are also output through the power buffer.

5 and 6 show operations according to a memory map and an address of the host computer, that is, the IBM-PC 4.

From the standpoint of the host computer (IBM-PC), the board's operation takes place by reading and writing data to a memory space that is not used by the IBM-PC (4).

That is, when the neural network board 1 is mounted on the IBM-PC 4 and the IBM-PC 4 designates an address of FIG. 5 that the IBM-PC 4 does not use, the neural network board 1 is specified. Perform the action.

The operating state of the neural network board 1 according to the address is as shown in FIG.

Here, the address is composed of 20 bits, which is the size of the memory address of the IBM-PC (4), and the upper four bits (indicated by n in FIG. 6) are the IBM- among the total memory of the IBM-PC (4) used. The empty memory space not used by the PC 4 can be arbitrarily used by the user.

In the present invention, the empty memory space is found and used.

The 'D address' shown in FIG. 5 and the four n shown in FIG. 6 are the same meaning as the upper four bits are empty.

5 shows a memory map, the configuration of which is as follows.

Prior to the description, the memory area, for example, 'DXXXX ₁₆ ' is omitted as 'DXXXX' and displayed.

Referring to FIG. 5, the memory area D40C0 of the "status register" is an area for storing the run signal states of the 36 DNP signals.

The memory areas D40A0-D40A7 of the "DNP selection register" are areas for selecting a DNP to which data or programs are to be uploaded / downloaded.

The memory areas D4080 and D4060 of the "status check (ORS, IRS)" are areas used to check communication flags of the six lowest PEs (0 to 5 PEs in FIG. 2). Here, when the state check (IRS) (D4060) address data is read, the PE selects a signal from the IRS pins (provided by the DNP chip) of the six PEs at the bottom, and the state check (ORS) (D4080). When reading the address data, the PE selects the signal from the ORS pin of the six PEs (provided by the DNP chip) at the bottom. Therefore, 36 DNPs can be arbitrarily selected using six of eight addresses.

Next, the memory area D4040-D4047 of the "data input / output (I / O)" is an area used for data communication between the host computer and the board while the board is operating when the system-wide operation is performed.

That is, only the six PEs at the bottom (the PE at the bottom in FIG. 2) can exchange data with the host computer during operation, and only the lower six addresses are used among the eight addresses in the D4040-D4047 area used for communication. Exchange data with each PE.

In addition, the memory area (D4020-D4027) of the "on-chip RAM" can read and write data to the RAM inside the DNP, and the eight addresses in this area are inside the PE. Used to store data in

The memory areas D4000-D401F of the "program RAM" can read and write programs to the RAM inside the DNP, and 32 addresses in this area are used for programming in the PE.

In the above, the PEs to which data or program is uploaded / downloaded should be determined in advance, and the address used for up / downloading of program and data of designated PEs correspond one-to-one with RAM address in the PE so that the address of host computer As it increases (the lower 6 bits of the total 20 bits are used), the address of the RAM increases sequentially in the PE.

The memory area D0000-D3FFF of the "off-chip RAM" is an area in which the board 1 reads and writes external data RAM in each module.

That is, as shown in FIG. 6, a value of 13-8 bits (denoted as 'd') is an address (0 to 35) of each module shown in FIG. 2, and the lower 7-0 bits (as 'a'). Denotes an address in one RAM selected from the 13-8 bits.

The PE can use 256 bytes of RAM.

Accordingly, the present invention uses two commands, PEEK (address) and POKE (address, data), to find and use an empty area of the memory area, where POKE and PEEK represent commands used by the IBM-PC (4). will be.

In other words, if you use the command PEEK (DXXXXh) (where h is 4 bits, ie hexadecimal), the FFh value comes out because the area is not used by IBM-PC (4).

If you execute POKE (DXXXXh, AAh; Write AA value to DXXXXh) command and PEEK (DXXXXh), FFh comes out because there is no memory.

However, the value of AAh is carried on the AT bus (or XT bus) when the POKE command is used.

Thus, the present invention is designed to take this value from the I / O interface (see reference numeral 3 in FIG. 1) of the neural network board mounted on the AT-bus (or XT-bus).

This region is defined and used as shown in FIG. 5 and FIG. 6 (where FIG. 6 is omitted since FIG. 5 and FIG. 6 have the same meaning).

Therefore, an example in which each component in FIG. 4 uses a code and a memory area will be described with reference to FIGS. 5 and 6 as follows.

Here, POKE (write) and PEEK (read) are instructions used by the IBM-PC 4, and the decoder 21 decodes the address and data values from the two instructions.

That is, the decoder 21 of FIG. 4 decodes each code input as follows.

First, in the status register D40CO, if the command coming from the IBM-PC 4 through the fourth buffer 14 is POKE (D40C0h, 1), the fourth selector 41 executes 36 DNP signals. If the (RUN) signal is set to '1' and POKE (D40C0h, 0) is set, the RUN signals of 36 DNP signals are set to '0'.

Here, the RUN signal is a signal for bringing the DNP into an on-line / off-line (RUN = 1 / RUN = 0) state. If RUN = 1, the DNP is performed as an instruction in the program memory.

Second, in the DNP selection registers D40A0-D40A7, sixty six out of eight addresses can be used to select 36 DNPs arbitrarily.

Similarly to the above, if the incoming command is POKE (D40A0h, 3Fh), the first selector 43 selects DNPs 0 to 5 (see 8 in FIG. 2) of FIG.

When the command is POKE (D40A0h, 0Fh), DNPs 2 through 5 in FIG. 2 (see 8 in FIG. 2) are selected by the first selection unit 43, and the command is POKE (D40A0h, 30h), the first and second DNPs 8 of FIG. 2 are selected by the first selector 43, and if the command is POKE (D40A1h, 3Fh), the DNPs 6 to 11 of FIG. 8) is selected by the first selector 43.

In this way the status register is used.

Here, when the DNP selection register and the status register are used, the value of the IBM-PC 4 is the value of the neural network board 1 when the register of the neural network board 1 is used. It enters a register, and its input value is held until there is a change.

The reason for this is called register because it keeps the input value.

In addition, the status register can put the board into an active state or an inactive state. If the bit 0 on the data bus is 1, the board is made operational; if 0, the board is made inoperable.

Third, in the state check (ORS, IRS) (D4080, D4060), if the incoming command is PEEK (D4080h) as above, the ORS of the DNP (ORS signal is sent from the DNP from 1 to 5 in FIG. 2). Signal) is read by the IBM-PC 4 through the fourth buffer 14, the first communication unit 31 and the third communication unit 33.

In addition, if the command is PEEK (D4060h), the IBM-PC (4) and the fourth buffer (14) are used by the IBM-PC (4) to transmit the IRS (IRS signal of the DNP to the outside) of the DNP from 1 to 5 in FIG. 1 Read through the communication unit 31 and the third communication unit (33). This state check area is used to check the communication flags in the six lowest PEs.

That is, when reading data in the status check (IRS) area, signals from the IRS pin (provided by the DNP chip) of the six lowest PEs are read, and when reading data in the status check (ORS) area, the ORS pin (provided by the DSP chip). You can see the signal from.

In other words, the IRS and ORS values indicate the operational state of the PE communication.

Fourth, in the data input / output (I / O) (D4040-D4047), if six out of eight addresses use the same instruction as above, POKE (D4040h), the input / output port ( IBM-PC (4) is read through the second communication unit 32 and the fourth buffer (14).

This data input / output area is used for data communication between the host computer and the board while the board is operating.

And PEEK (D4040h, Ah) sends Ah value to the input / output port of DNP No. 0 in FIG.

If the incoming command is POKE (D4041h), the IBM-PC 4 reads the data in the input / output port of DNP No. 1 in FIG. 2 through the second communication unit 32 and the fourth buffer 14.

PEEK (D4041h, Ah) sends Ah value to the input / output port of DNP No.1 in FIG. 2, and POKE (D4045h) sends the data at the input / output port of DNP No.6 in FIG. 2 to IBM-PC (4). Is read through the second communication unit 32 and the fourth buffer 14, and PEEK (D4045h, Ah) sends Ah value to the input / output port of DNP No. 5 in FIG.

The same applies to DNPs 2, 3 and 4 below.

Fifthly, in the on-chip RAM D4020-D4027, data can be read and written to eight memory areas.

As mentioned above, reading is PEEK and writing is POKE.

This memory area can contain variables necessary for executing a program (program of neural network model), and can store other necessary values.

Before this instruction can be used, the DNP which wants to be uploaded by the IBM-PC 4 must be selected using the DNP select register code.

Sixth, in the program RAM D4000-D401F, the program is loaded by the IBM-PC 4 in 32 areas.

A program is a program of a neural network model written in DNP machine code. As you write this program, the DNP will do what you want.

For example, software for text recognition may be raised and software for speech recognition may be raised.

Before the instruction as mentioned above is used, the DNP which wants to be uploaded by the IBM-PC 4 is selected using the 'DNP select register' code.

Seventh, in the off-chip RAM (D3FFF-D0000), data can be read and written to each off-chip memory (see reference numeral '6' in FIG. 3) in this area.

As mentioned above, the reading is PEEK and the writing is POKE.

In the off-chip RAM code of FIG. 6, 6 d are decoded to select 36 memories each, and 8 a denote 256 addresses.

An example of this is as follows.

If POKE (D0000h, O0h) is used, 00h writes the value to 0 of the off-chip memory which is with DNP No. 2 in FIG.

Suppose that POKE (D0001h, 00h) writes a value of 00h to address 1 of the off-chip memory which is located with DNP No. 2 in FIG.

In the case of POKE (D00FFh, AAh), the value of AAh is written in the FF address of the off-chip memory with DNP No. 2 in FIG.

If POKE (D0100h, 00h) is used, 00h is written to address 0 of the off-chip memory in the same manner as DNP No. 1 in FIG.

If POKE (D1F00h, 00h) is written, 00h value is written in 0 of the off-chip memory which is with DNP of FIG.

Other than that is used in the same way.

Code descriptions of FIGS. 5 and 6 associated with the selection section are as follows.

The data I / O status check code consists of two types of IRS and ORS signals coming from the DNP chip. The purpose of these signals is to communicate data between the processor board and the IBM-PC on-line. This is a signal to enable.

Using this code, the IBM-PC knows the IRS and ORS signals from the 0-5 processor (DNP) in Figure 2, and you can use it to verify the processor board's operation.

The 'data I / O' code is related to the above-mentioned IRS and ORS signals, and reads the data sent to the IBM-PC by the processor (only processor 0 to 5 of FIG. 2 performs this operation). .

That is, when the value of this code is loaded on the address bus of the IBM-PC, the board decodes the data sent by the processor on the data bus to the IBM-PC.

Check whether there is data sent by using IRS or ORS.

If the processor sends data to IBM-PC, the ORS is set to 1, otherwise it is set to 0.

Conversely, when a processor attempts to receive data, it sets the IRS to 1 to inform IBM-PC that it is ready to receive data.

In addition, the 'status register' code controls the overall operation of the board (RUN signal of DNP).

Accordingly, the operation of the board is as follows.

First, select the chip or memory to download the program and data (use uploading for testing).

Then, when the downloading of the desired data is completed, the program is executed, and if necessary, the communication units perform on-line communication.

When the program execution is completed, the chip may be selected or the memory may be selected again to load the program or data again.

Alternatively, the program can be executed by re-downloading the program and data in the currently selected state.

Here, the on-line state is a state in which the program memory of the DNP is performed, and when the execution of the program memory is completed, the result is sent to the IBM-PC (4). have.

In contrast, the off-line state carries data in the program memory and data memory of the processor in the IBM-PC 4 (off-chip RAM, program RAM, on-chip RAM).

Or, to verify the result, the IBM-PC 4 reads data from the processor.

Each DNP has its own program memory, so every DNP can perform its own operation.

When the processor is in such a state that it can operate, it moves to the next state, the on-line state, to execute the program.

The overall system operation is as follows.

The data of the off-chip RAM, the program RAM, and the on-chip RAM shown in FIG. 6 are loaded into the RAM of the E-MIND board, which is a neural network board.

Thereafter, the boards are activated by activating the signals of the chip select (CS) and the operation (RUN) of the DNP chip.

Then, the board executes the program in the order stored in the program RAM of the DNP.

At this time, if the data necessary for the program execution is in the off-chip RAM or on-chip RAM, it is read from the IBM-PC 4 through the communication units 31 to 33 if necessary.

Accordingly, the operation of the entire system is performed as stored in the program of the DNP, and in particular, it can be advantageously operated for text recognition and voice recognition, and is effective for solving problems in neural network algorithms.

Then, deactivating the operation RUN and chip select CS stops the operation of the board.

As described above, the E-MIND board designed by the present invention has the following effects.

(1) The neural network models are characterized by high parallelism and a large amount of computation due to the parallelism. The E-MIND board is designed to have a parallel processor to satisfy these characteristics, thereby enabling real-time data processing.

(2) Since E-MIND board is implemented by using digitally designed DNP chip for MIMD, various neural network models can be simulated according to the program downloaded to PEs.

(3) The E-MIND board is compatible with IBM-PC, and 36 basic modules can be effectively controlled from IBM-PC.

(4) Depending on the software of the neural network model, the E-MIND board can perform various functions. Especially, it can be used for handwritten character recognition and number recognition.

Claims (2)

In a neural network board (1) comprising an interface device for controlling performance of data transmission between the IBM-PC (4) and the MIMD type parallel processor (2), 36 parallel processors (2) are raised by raising a clock (CLK) signal. ), The first buffer 11 for distributing without time delay, the second buffer 12 for making the input / output wait number (IO-RDY signal) of the AT-bus entering the IBM-PC 4, and the IBM-PC ( A fourth buffer 14 which connects the AT-bus and the processor board of 4) to exchange memory write / read signals, data signals, address signals, and drive resets (DRV-RESET) with the IBM-PC (4); The third buffer 13, which is a power buffer for raising the signal output from the fourth buffer 14 and sending it to the decoder 21, and the memory output from the fourth buffer 14 and in the parallel processor 2 From the AT-bus (or XT-bus) of the IBM-PC 4 via a fifth buffer 15 for outputting write and read control signals and the fourth buffer 14; Is a decoder 21 for decoding an address and a data value, and a first selector for generating a signal for selecting a DNP chip in the parallel processor 2 by a signal decoded using the DNP selection register code in the decoder 21. (43), a fourth selector (41) which receives a signal decoded by the decoder (21) and selects a RUN or RESET signal for operating the parallel processor 2, and the decoder ( A fifth selector 42 which receives the decoded signal 21 and generates a RAM operation signal of the parallel processor 2, a RUN signal state selected by the fourth selector 41, and a fifth The second operation unit 44 which combines the memory operation signals selected by the selection unit 42 to output the memory selection signal RAM_CS to the parallel processor 2, and the RAM operation signal selected by the fifth selection unit 42. Receive the parallel using the DNP chip selection signal (DNP_CS) selected by the first selector 43 A third selector 45 for outputting a buffer enable signal BUF_EN to the processor 2 and the decoder 21 when the parallel processor 2 and the IBM-PC 4 are in an on-line state. A first communication unit for receiving the flag state of the data input / output status check value of the DNP through the fourth buffer 14 and causing the PC 4 to read the data input / output status check (IRS, ORS) code as a result of decoding. 31) and the data input / output of the DNP according to the result of the decoding of the data input / output state check (IRS, ORS) code by the decoder 21 when the parallel processor 2 and the IBM-PC 4 are in the on-line state. When the flag state of the state check value is set to the flag state value, parallel with the third communication unit 33 which causes the IBM-PC 4 to read the set value from the parallel processor through the fourth buffer 14. When the processor 2 and the IBM-PC 4 are in an on-line state, the data input / output code is decoded by the decoder 21. The second communication unit 32 configured to allow the IBM-PC 4 to read or write data in the input / output port of the DNP through the fourth buffer 14 according to the coded result; Universal neural network board that can be connected and used. The general purpose neural network board according to claim 1, wherein the interface device is housed on the neural network board (1) and is integrally formed.