KR960000927B1 - High density bipolar 3 code - Google Patents

Abstract

The device comprises a clock generating unit which generates standard clocks, a pseudo signal generating unit which generates temporary signals to be used standard data necessary to generate errors, an error signals generating unit which generates error signals by clock signals from the clock generating unit, an error ratio selection and displaying unit which announces the selected error ratio by using a light emitting diode, an error signal inserting selection unit which determines the insertion of the error signals of the selected error ratio, a code converting unit which converts arbitrary signals to HDB3 code, and an output unit which converts unipolar HDB3 code to bipolar data and matches with transfer lines.

Description

High-density-bipolar 3 (HDB3) code error generator

1 is an overall block diagram of the present invention.

FIG. 2A is a detailed circuit diagram of the clock generator 10 of FIG.

(b) is a detailed circuit diagram of the pseudo signal generator 20 of FIG.

(c) is a detailed circuit diagram of the error signal generator 30 of FIG.

(d) is a detailed circuit diagram of the error rate selection and display unit 40 of FIG.

(e) is a detailed circuit diagram of the error signal insertion selector 50 of FIG.

(f) is a detailed circuit diagram of the code conversion unit 60 of FIG.

(g) is a detailed circuit diagram of the output unit 70 of FIG.

* Explanation of symbols for main parts of the drawings

10: clock generator 20: pseudo signal generator

30: error signal generator 40: error rate selection and display unit

50: Error signal insertion selector 60: HDB3 encoder

70: output unit 11: multivibrator

12, 13: D flip-flop 21, 23: XOR gate

22: Oagate 24, 25: counter

31-36: Counter 37-42: D flip flop

43-49: NANDGATE 50-55: ANDGATE

401: selector SW2: switch

LED1-LED3: Light Emitting Diode 501: Multivibrator

502: D flip-flop 503: end gate

505, 506: NAND gate 504, 508: inverted gate

507: Oagate 60: HDB3 Code Converter

71, 72: XOR gate 73, 74: D flip flop

75 Transmitter C1-C7 Capacitor

VR1: Variable resistance X1: Crystal

L1: Inductor R1-R5: Resistance

The present invention provides a communication transmitter and receiver using a high density bipolar 3 (HDB3) code, in which an input signal receiver does not use a measuring instrument to measure the reception performance of the receiver. It's about an HDB3 code error generator that allows you to insert errors.

HDB3 code is an abbreviation of 'HIGH DENSITY BIPOLAR 3'. It is a code generated by inserting '1' according to a certain rule when more than four '0's appear in a certain data. Used in relays, multiplexers, etc.

Therefore, the communication line installed by using the European-type communication equipment as described above generates an HDB3 error code at the transmitting side in order to check whether there is an abnormality in the transmission / reception line, and then determines the situation where the error code is received at the receiving end. In this case, conventionally, an error code is generated by using a complicated measuring instrument, but the measuring equipment itself is quite expensive, and there is a problem in that it is very complicated in terms of usage.

Accordingly, an object of the present invention is to design and configure an HDB3 code error generator using a plurality of IC devices and electronic components in view of the above-described problems, and to provide an HDB3 code error generator that can easily localize expensive measurement equipment and use it. Is in.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a schematic block diagram of the HDB3 code error generator of the present invention, which includes a clock generator 10 for generating a standard clock (2048 kbps + 50 ppm) required for the HDB3 code error generator, and the clock generator 10 from the clock generator 10. FIG. A pseudo (PSEUDO) signal generator 20 for generating an arbitrary signal to be used as reference data necessary for generating an error by inputting a clock signal, and a clock signal from the clock generator 10 as an input. An error signal generator 30 for generating an error signal having an arbitrary magnification with respect to the arbitrary data output from the upper pseudo signal generator 20, divided by 10e-1-10e-6, and the error signal generator ( An error rate selection and display unit 40 which selects an error from an error signal having an arbitrary rate generated in 30) and informs the selected error rate to the outside using the light emitting diodes LED1-LED3, and in the error rate selection and display unit 40 Error signal of determined error rate An error signal insertion selector 50 for determining whether to insert a?, A code converter 60 for converting an arbitrary signal output from the pseudo signal generator 20 into an HDB3 code, and the coded random And an output unit 70 which carries an error signal to the data, converts the unipolar HDB3 code into bipolar data, and outputs it to the transmission line.

A detailed circuit diagram of each part of the present invention configured as described above is shown in (a) to (b) of FIG. 2, and the operation and effect of the present invention will be described in more detail below.

FIG. 2A is a detailed circuit diagram of the clock generation section 10 according to the present invention. The voltage controlled multivibrator 11 outputs a stable oscillation signal by a crystal X1 of 8.19 MHz, and the multivibrator. And the D flip-flops 12 and 13 for dividing the signal oscillated in (11) into a 2.048 Mbps digital clock required for each part of the present invention. The operation is oscillated from the crystal (X1) and the multivibrator (11). The digital clock of 8.192 Mbps outputted from) is divided by 1/2 by the D flip-flop 12 to output a clock of 4.096 Mbps, and the output clock of 4.096 Mbps is again 1 / d by the D flip-flop 13. Divided by 2, a clock of 2.048 Mbps required by each part of the present invention is formed.

FIG. 2B is a detailed circuit diagram of the pseudo signal generator 20 according to the present invention. The gate 21, 22, 23 for forming the start of arbitrary data generation and the generated signal are shown in FIG. It consists of shift registers 24 and 25 for shifting and feeding back feedback in synchronization with the digital clock generated by (a) and outputting arbitrary data. 24 and 25 are inputted to the clock terminal CLK and shifted 8 bits in the shift register 24, and are simultaneously inputted to the input terminals A and B of the shift register 25 and shifted again. A signal shifted by (8 + 6) bits and (8 + 7) bits is fed back to the XOR gate 23 and the oragate 22 connected to the output terminals 01 and 02, respectively. From the XOR gate 21 to which the resistor R2 and capacitor C4 connected to the supply voltage (+ 5V) Logic is formed with the output of and is inputted back to the input terminals C and D of the shift register 24 and output at the same time to generate random data.

FIG. 2C is a detailed circuit diagram of the error signal generator 30 in the present invention, and includes counters 31-36 for counting a 2.048 Mbps digital clock output from the clock generator 10. It consists of a D flip-flop 37-42 and an AND gate 50-55 and a NAND gate 43-49 that latch and output the output from each counter 31-36 once. same.

That is, the 2.048 Mbps reference clock generated from the clock generator 10 is applied to the clock input terminal CK of the counter 31, and the counter 31 counts the clock to digital 1000.

Finally, when the count reaches 1001, the output terminals A and B become high and the high signal is applied to the AND gate 51 and the NAND gate 44 connected to the output terminals A and B.

The output of the AND gate 51 is applied to the clock terminal CK of the next counter 32 as one clock, and the output of the NAND gate 44 is applied to its clear terminal CLR again. A signal is applied to the clock terminal CLK of the D flip-flop 37 at the same time as clearing the count initial value of.

As described above, the D flip-flop 37 can output by dividing the output divided by 1/10 by the first counter 31, and the clock is applied to the counter 32 of the next stage to divide 1/10. The applied output can then be divided and output again.

Therefore, the divided clocks are formed at the magnification of 10e-1 to 10e-6 by the output of each D flip-flop 37-42, and the error rate of the divided data is determined. It serves as a basis for forming the data of the error rate.

FIG. 2D is a detailed circuit diagram of the error rate selection and display unit 40 according to the present invention, in which a switch SW2 set for selecting an error rate and an error rate selected by the switch SW2 are indicated. It consists of a light emitting diode (LED1-LED2), the function is as follows.

That is, the user selects and sets the error rate selector switch SW4 as a binary value of 3 bits, and the set value is decoded by the data selector 401 to be connected to the input terminal of 10e-1 to 10e-6. One output is selected from the error rate.

In this case, when the error rate is selected by switching, the light emitting diodes LED1 to LED3 connected in series with the switch SW4 are also turned on to inform the user of the switched state.

FIG. 2E shows an error signal insertion selector 50 according to the present invention, which outputs a delayed clock signal which is divided at an arbitrary rate selected by the error rate selection and display unit 40 for a predetermined time. A counter 502 for dividing the digital clock of 2M from the multivibrator 501 and the clock generator 10 by 1/2, a switch SW1 and a NAND gate 505, 506 for determining whether an error is inserted; And an AND gate 503, inverting gates 504 and 508, which form a logic to output data delayed by the 1/2 divided signal when an error insertion is determined by the switch SW1. It consists of a gate 507, the function of which is as follows.

The randomly divided clocks selected and output by the error rate selection and display unit 40 are inputted to the multivibrator 501 by a time constant determined by the resistor R5 and the capacitor C5 connected to the multivibrator 501. The output is delayed.

At the same time, a 2M reference clock is applied to the D flip-flop 502 and divided into 1/2 outputs. The clock signal of any divided error rate is delayed and output by the 1/2 divided reference clock and the multivibrator 501. The clock signal of any divided error rate ended and output from the AND gate 503 serves as an error signal of the actual error rate.

At this time, when the switch SW1 is in the first state, the normal data output state is entered, and in the third state, the error data is inserted.

FIG. 2 (f) is a detailed circuit diagram of the code conversion unit 60 in the present invention, which is configured by using an HDB3 code converter 60. The code converter 60 is a transcoder, and the reference clock is a terminal. When supplied to (CTX) and arbitrary data is input to the terminal NRZ-IN, HDB3 is coded and output to the output terminals HDB3 OUT + and HDB OUT-.

FIG. 2 (g) is a detailed circuit diagram of the output unit 70 according to the present invention, in which an arbitrary data signal coded at the time of the error signal insertion determination by the switch SW1 of the error signal insertion selection unit 50 is determined. Exclusive OR gates 71 and 72 for inserting an error signal and D flip-flops 73 and 74 for latching and outputting error data output from the XOR gates 71 and 72 once; Transmitter 75 converts the output unipolar data into bipolar data and outputs the same.

That is, an error signal generated and output from the coded HDB3 DATA + and DATA + and the error bit insertion selector 50 is input to the XOR gates 71 and 72, and the XOR gates 71 and 72 insert the error bit. The switch SW1 of the selector 50 outputs a signal into which an error signal is inserted when an error is inserted.

The error-inserted HDB3 DATA + and HDB3 DATA-signals are input to the transmitter 75 through respective D flip-flops 73 and 74, and the transmitter 75 converts the input unipolar data signal into bipolar data. By outputting through the output terminal (TX-OUT), generation of the HDB3 error code is completed.

As described above, the code error generator of the present invention has the effect of localizing expensive measurement equipment by designing and configuring a plurality of devices and electronic components and making it easy for anyone to use.

Claims (8)

A clock generator 10 generating a standard clock (2048kbps + 50ppm) and a pseudo signal generating an arbitrary signal to be used as reference data necessary for generating an error by inputting a clock signal from the clock generator 10 (PSEUDO). A signal generator 20, an error signal generator 30 for dividing a clock signal from the clock generator 10 to generate an error signal at a predetermined error rate, and the error signal generator 30 An error rate selection and display unit 40 which selects a specific error rate among the error signals having a random rate generated and notifies the selected error rate to the outside using a light emitting diode, and an error signal of the error rate selected by the error rate selection and display unit 40. An error signal insertion selector 50 for determining whether to insert the code, a code changer 60 for converting an arbitrary signal output from the pseudo signal generator 20 into an HDB3 code, and the coded random code. HDB3 code error generator, characterized in that the stage consisting of the HDB3 code carries an error signal to the other polarity to the output section 70 a to be the matching with a transmission line and at the same time converted into bipolar data. The clock generation unit (10) according to claim 1, wherein the clock generator (10) sees a voltage controlled multivibrator (11) outputting a stable oscillation signal by a crystal (X1) of 8.192 MHz, and a signal oscillated by the multivibrator (11). An HDB3 code error generator characterized by comprising D flip-flops (12, 13) divided by a 2.048 Mbps digital clock required for each part of the invention. 2. The pseudo signal generating unit 20 according to claim 1, wherein the pseudo signal generating unit 20 includes a gate (21, 22, 23) resistor (R2) and a capacitor (C4) for forming a start signal of arbitrary data generation, and the generated signal to a digital clock. An HDB3 code error generator comprising two shift registers (24, 25) for synchronously shifting and feeding back and outputting arbitrary data. The error bit generator (30) according to claim 1, wherein the error bit generator (30) counts a digital clock of 2.048 Mbps output from the clock generator (10) from the counters (31-36). The output of the HDB3 code error generator, characterized in that consisting of the D flip-flop (37-42) and the end gate (50-55) and the NAND gate (43-49) to output once latched. 2. The error rate selection and LED display unit 40 according to claim 1, wherein the error rate selection and LED display unit 40 is set to select an error rate, and data of the error rate selected by the switching among the errors output from the error bit generation unit 30. HDB3 code error generator, characterized in that consisting of a data selector (401) for outputting a light emitting diode (LED1-LED2) for displaying the selected error rate. The multivibrator 501 of claim 1, wherein the error signal insertion selector 50 divides the clock signal outputted by the random rate output from the error rate selection and display unit 40 by a predetermined time and outputs the delayed signal. A counter 502 for dividing the 2M digital clock from the clock generator 10 by half, switches SW1 and NAND gates 505 and 506 for determining whether to insert an error, and the switch SW1 Is composed of an AND gate 503, an inverting gate 504, 508, and an oragate 507 which form a logic to output the delayed data by the 1/2 divided signal when the error insertion is determined by HDB3 code error generator, characterized in that. The XOR gate 71 of claim 1, wherein the output unit 70 inserts an error signal into arbitrary data coded at the time of error bit insertion switching from the error signal insertion selector 50. 72) and D flip-flops 73 and 74 for latching and outputting error data output from the XOR gates 71 and 72, and a transmitter for converting the output unipolar data into bipolar data and outputting the bipolar data. 75) HDB3 code error generator, characterized in that consisting of. 6. The HDB3 code error generator according to claim 1 or 5, wherein the error rate is selectable from 10e-1 to 10e-6.