AU627388B2

AU627388B2 - Additional signal transmission in a transmission system for digital signals with a high bit rate

Info

Publication number: AU627388B2
Application number: AU68153/90A
Authority: AU
Inventors: Gerhard Thanhaeuser; Annemarie Wipf
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1989-12-18
Filing date: 1990-12-17
Publication date: 1992-08-20
Anticipated expiration: 2010-12-17
Also published as: EP0433706A2; EP0433706A3; DE59008970D1; EP0433706B1; AU6815390A; ATE121893T1

Abstract

According to a prior patent application, the digital user data signal is transmitted in CMI code and, when the code is generated, a binary signal content of the auxiliary signal is allocated to one of the element combinations excluded according to the CMI code rule. Only the start of a one bit or zero bit of the auxiliary signal is marked, so that needle pulses occur at the receiving end at comparatively large intervals only, which pulses are adequate for transmission of the auxiliary signal but severely impede generation of a clock signal at the receiving end. According to the invention, a combination signal is therefore transmitted which contains a clock pulse pattern for simple generation of a clock signal at the receiving end. <IMAGE>

Description

4. The basic application(s) referred to in paragraph 2 of this Declaration was/we e-the first application() made in a Convention country in respect of the invention the subject of the application.

Declared at Sydney this 11 day of October 1990 0 1E i, i;.

j; :F- SFP4 To: The Commissioner of Paten r ts Signature of Declarant(s) 11/81 iS 4i S F Ref: 140562 FORM COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 COMPLETE SPECIFICATION

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FOR OFFICE USE: Class Int Class

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*art I C e I I C Complete Specification Lodged: Accepted: Published: Priority: Related Art: Name and Address of Applicant:

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Siemens Aktiengesellschaft Nittelsbacherplatz 2 D-8000 Munchen 2 FEDERAL REPUBLIC OF GERMANY Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia Address for Service: Complete Specification for the invention entitled: Additional Signal Transmission in a Digital Signals with a High Bit Rate The following statement is a full description best method of performing it known to me/us Transmission System for of this invention, including the 5845/3

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Ii 89 P 2022 DE Abstract i Additional signal transmission in a transmission system i for digital signals with a high bit rate In accordance with an earlier patent application, the digital wanted signal is transmitted in the CMI code, and during the generation thereof a binary signal content of the additional signal is assigned to one of the element combinations forbidden according to the CMI code rule. With this method, only the beginning of a one-bit or of a zero-bit of the additional signal is marked so that needle pulses occur at the receiving end only at comparatively great intervals, which pulses, although sufficient for transmnitting the additional signal, make the generation of a clock signal much more difficult at the receiving end. According to the invention, therefore, a combined signal is transmitted which contains a clock pulse grid for easy generation of a clock signal at the receiving end. Fig. 2

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1A- 89 P 2022 DE Siemens Aktiengesellschaft Additional signal transmission in a transmission system I for digital signals with a high bit rate The invention relates to a method for transmitting a digital additional signal in accordance with the preamble of Claim 1 and an arrangement for carrying out i the method.

A transmission system for digital signals with a high modulation rate is known from DE-A1-3 330 683, ir which a signal of comparatively low modulation rate is also transmitted additionally. In the line terminals the known transmission system contains code converters which convert the digital wanted signal to be transmitted into the actual transmission code at the transmitting end and convert it back at the receiving end. In the code converter at the transmitting end the clock signal required is generated by means of a phase-locking loop, and for trans- Smitting the additional signal the control voltage of the phase-locking loop is additionally amplitude-modulated and hence, via the clock signal, the signals output to the link are phase-modulated. At the receiving end the t, phase discriminator contained in the phase-locking loop for the clock generation also acts as a demodulator for the additional signals which can be picked up at the phase discriminator output.

As a result of the limited transmission capacity owing to a limited phase-angle deviation permitted, a method described in German Patent Application P 39 39 640.1 was developed in which the wanted signal is transmitted in the CMI code, and in the generation of which at least one of the element combinations forbidden according to the CMI code rule is assigned a binary signal content.

In order to disturb the transmission of the wanted signal as little as possible, in this method only the beginning of a one-bit or of a zero-bit of the additl, nl signal is marked. The additional signal is transmitted here by redundant coding and violation of the code rule, the -2violation being made in such a way that at the receiving end it is possible to distinguish between code rule violations caused by interference and the code rule violations for transmitting the additional signal. As a result of the assignment of in each case one code rule violation to one bit of the additional signal, which has a very low bit rate in comparison to the wanted signal, a data pulse is produced which is extremely narrow in relation to the period duration of the associated clock signal. In order to be able to realize a transmission system in this manner without using a scrambling device, it would be possible, For ensuring the clock generation at the receiving end, to use a redundant code, for example a two-phase code in the form of the known CDC or the Manchester code, which also provides a sufficient number of signal changes for clock regeneration even with NRZ signals and with continuous zero or a continuous one. However, the aforesaid codes require at least a half-bit wide transmission of one-bits and are hence not readily suitable for a method with extremely narrow data pulses. Also, the use of a mono-flop for pulse expansion leads to increased expenditure, since the position of the trailing pulse edge in the bit grid must be maintained very precisely due to the risk of a high character distortiion, 20 and this cannot be expected of a mono-flop alone.

The object of the present invention is therefore to provide a possibility for additional signal transmission in which it is possible to generate a clock signal for the additional signal at the receiving end without great outlay.

In accordance with one aspect of the present invention there is disclosed a method for transmitting a digital additional signal with a comparatively low bit rate, together with the digital wanted signal S; transmitted in one channel of a digital transmission system, by insertin the additional signal during the coding of the binary wanted signal int o a transmission or link code, said method comprising the steps of: combining the digital additional signal and a clock signal associated therewith, to form a combined signal, the bit rate of which corresponding to that of the additional digital signal to be transmitted, and generating a clock pulse, comparatively short with respect to the bil period of the combined signal at the beginning of each bit of the C /1531 0 44 -2Acombined signal and, at the fixed time intervals from the generation of said clock pulse, generating a data pulse whenever a bit with a given logical level begins in the digital additional signal.

in this method, the generation of a combined signal from the digital additional signal and the associated clock signal provides a high degree of reliability during the detection of the clock phase at the receiving end for comparatively little outlay at the transmitting end.

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ments of the -met-hod according to theinvent described in Patent Claims 2 to 4. mparatively inexpensive and easily i tegr ed arrangement for carrying out teae d according to the invention is descried in Patent Claims-5- to 7.

The invention will be described in greater detail below with reference to an exemplary embodiment illustrated in the drawing, in which: Fig. 1 shows a timing diagram of the combined signal generated from the additional signal and the associated clock signal, and Fig. 2 shows a circuit arrangement for generating the combined signal according to Fig. 1.

The pulse diagram illustrated in Fig. 1 shows the combined signal generated, which is transmitted together with the digital wanted signal by intentionally generated code rule violations during the code conversion of said digital war,ited signal. The combined siignal has a bit rate corresponding to that of the digital additional signal with the bit duration T. At the beginning of each bit of the combined signal, the latter contains a clock pulse TP which is comparatively very short in comparison to 1/4 of the bit duration T so that the combined signal has a fixed clock pulse grid which can be easily evaluated at 25 the receiving end for generating a new clock signal. For transmitting the additional signal information, a data pulse DP can be inserted at an interval of approximately 1/4 bit period T into the clock pulse grid following the clock pulse, the length of which data pulse corresponds approximately to that of the clock pulses TP. The duration of the clock and data pulses is comparatively short in comparison to the time interval between directly successive clock and data pulses of approximately 1/4 bit period. In order to limit the number of code rule violations, a data pulse is only inserted if a bit begins with a given logical level in the digital additional signal.

It can be freely selected here whether only the beginning of binary one-bits or that of binary zero-bits is to be marked; owing to the easier detectability, that of binary jci c C 4C' (C CfL C

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fgA cc, i i 4 89 P 2022 DE one-bit was selected in the exemplary embodiment. The second data bit DP2 thus indicates the beginning of a binary one-bit of the digital additional signal. The interval of approximately 1/4 bit period T between clock pulse and data pulse is not critical in this case; it was selected in order to be able to regenerate the one-bits of the additional signal in the original length more easily at the receiving end, and also in order to permit a reliable distinction between clock and data pulses at the receiving end in the case where there is comparatively large phase jitter of the data pulses.

The circuit arrangement shown in Fig. 2 for generating the combined signal illustrated in Fig. 1 S< cont,%ins two series circuits each beginning with a D-type flip-flop. In the upper series circuit, the data pulses ,DP are generated, and the clock pulses TP are generated in the lower series circuit; both are combined in the NAND gate at the output side so that the desired combined signal is present at the output terminal A thereof.

The upper circuit part contains a first D-type flip-flop DF1, the D input of which is connected to the input DE for the digital additional signal, and the i inverting output of which is connected to the Lr int input of a binary counter BZ. The clock input of the binary C 25 counter BZ designed as 4-bit counter is connected to the output terminal of an oscillator OS which oscillates at C "32 times the bit frequency of the digital additional signal. The output terminal of the 4-bit counter BZ for the highest counter position 3 is connected via a first 30 inverter Ii to a first input of the NAND gate NAND, and via a first resistor R1 to the reset input R of the first D-type flip-flop DF1, and also via a first capacitor Cl to reference potential.

The lower circuit part for clock pulse generation contains a second D-type flip-flop DF2, the clock input of which is connected to the clock input of the first Dtype flip-flop DF1, and also to an input TE for a clock signal corresponding to the signal at the input DE. The D input of the second D-type flip-flop is connected to I' 5 89 P 2022 DE the inverting output thereof; the clock input of a third D-type flip-flop DF3 is connected to the non-inverting output, the D input of which flip-flop is connected to a terminal H for a potential corresponding to the logical high level, and the non-inverting output of which is connected via a second resistor R2 to the input terminal of a second inverter 12, and also via a second capacitor C2 to reference potential. The output terminal of the second inverter 12 is connected to a second input of the NAND gate NAND, and also to the reset inputs R of the second and of the third D-type flip-flop DF2, DF3. The NAND gate NAND contains a third inverter 13 connected to the first input terminal thereof, and a fourth inverter 14 connected to the second input terminal thereof; the output terminals of both inverters are connected to the output terminal A to form an OR circuit.

The clock pulse generation in the lower circuit part is triggered by the leading edge of the clock signal present at the input terminal TE, as a result of which the second D-type flip-flop DF2 is set to the logic level 1. 'le non-inverted output signal of the second D-type flip-flop DF2 clocks the third D-type flip-flop DF3, the delayed output pulse of which resets both D-type flipflops DF2, DF3. The delay is brought about here by the RC delay element formed by the second resistor and the second capacitor, and by the second inverter 12. The resulting width of the pulse generated is thus the sum of one flip-flop delay, the delay in the RC element and the delay through the inverter. The combination of two D-type flip-flops DF2, DF3 was provided for matching the delays of clock pulse generation and data pulse generation.

The data pulse generation in the upper circuit part is likewise triggered by the leading edge of the input clock which enables the downstream 4-bit binary counter BZ when a one-bit is present in the data signal.

The free-running oscillator OS with a frequency of approximately 32 times the frequency of the clock signal at the input TE clocks the binary counter BZ. After seven 6 89 P 2022 DE to eight periods of the oscillator output signal, analogously to the clock pulse generation, the first D-type flip-flop DF1 and the binary counter BZ are reset, delayed by the first inverter Ii, so that a resulting pulse of approximately equal width to the clock pulse generated in the lower circuit part is produced. The relative phase position between input clock and oscillator clock determines the delay during the insertion of the data pulse relative to the respective clock pulse. In accordance with 7/32 or 8/32, the insertion is carried out approximately 0.22 T to 0.25 T after the clock pulse.

With plesiochronous operation of the oscillator OS in relation to the clock signal at the input TE, a data pulse DP with jitter can be produced. However, this jitter is not critical since no clock signal is derived from the data pulses at the receiving end, but rather is formed as described solely from the clock pulse grid.

The receiving end co-operating with the transmitting end described is described in a parallel patent application.

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Claims

1. A method for transmitting a digital additional signal with a i comparatively low bit rate, together with the digital wanted signal transmitted in one channel of a digital transmission system, by inserting the additional signal during the coding of the binary wanted signal into a transmission or link code, said method comprising the steps of: combining the digital additional signal and a clock signal associated therewith, to form a combined signal, the bit rate of which corresponding to that of the additional digital signal to be transmitted, and generating a clock pulse, comparatively short with respect to the bit period of the combined signal, at the beginning of each bit of the combined signal and, at the fixed time intervals from the generation of said clock pulse, generating a data pulse whenever a bit with a given logical level begins in the digital additional signal.

2. A method according to claim 1, wherein 'the data pulse is generated whenever a binary one-bit occurs in the digital additional signal.

3. A method according to claim 1, wherein in that the data pulse is generated whenever a binary zero-bit occurs in the digital additional signal.

4. A method according to any one of claims 1 to 3, wherein the data pulse is generated at a time interval of approximately a 1/4 bit period following the clock pulse, and the duration of the data pulse and of the clock pulse is comparatively short in comparison to the time interval

5. An arrangement for carrying out the method according to any one of claims 1 to 4, said arrangemeo't comprising: a first D-type flip-flop, the D input of which is connected to Si an input for the digital additional signal, and the inverting output of L which being connected to the count input of a binary counter, the clock input of the binary counter being connected to output of an oscillator having an oscillating frequency corresponding to an integral multiple of the bit rate of the digital additional signal, the output of the binary counter being connected via a first inverter, firstly to a first input of. a NAND gate, and secondly, via a first resistor to the reset input of the first D-type flip-flop; /1531o i J i 8 I -8- a first capacitor connected between the reset input of the first D-type flip-flop and a reference potential; a second D-type flip-flop, the clock input of which being connected to the clock input of the first D-type flip-flop and to a clock signal input, the inverting output of the second D-type flip-flop connecting to the D input thereof and the non-inverting output connecting to the clock input of a third D-type flip-flop, wherein the D input of -the third D-type flip-flop is connected to a terminal asserting a J potential corresponding to the logical high level, and the non-inverting output of the third D-type flip-flop connecting via a second resistor, firstly to the input of a second inverter, and secondly to the one terminal of a second capacitor, the second terminal of the second capacitor being connected to the reference potential, wherein the output of the second inverter is connected to the reset inputs of the second and third D.-type flip-flops and also to the second input of the NAND gate, wherein the combined signal is output at the output of the NAND gate.

6. An arrangement according to claim 5, wherein the oscillator generates an oscillation having a frequency corresponding to 32 times the bit rate of the additional signal, and the binary counter is designed as a 4-bit countcr.

7. An arrangement according to claim 6, wherein the NAND gate !i S' contains a third inverter connected to the output of the first inverter, and a fourth inverter connected to the output of the second inverter, the output terminals of which are gated to an OR circuit, and the output of the OR circuit representing the output of the NAND gate.

8. A method for transmitting a digital additional signal substantially as described herein with reference to the drawings.

9. An arrangement for transmitting a digital additional signal substantially as described herein with reference to the drawings. DATED this FIRST day of JUNE 1992 Siemeis Aktiengesellschaft F AUs. Patent Attorneys for the Applicant -I C SPRUSON FERGUSON IAD/1531o L