KR950034693A - Method of forming semiconductor multilayer thin film metal wiring - Google Patents

Method of forming semiconductor multilayer thin film metal wiring Download PDF

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Publication number
KR950034693A
KR950034693A KR1019940011508A KR19940011508A KR950034693A KR 950034693 A KR950034693 A KR 950034693A KR 1019940011508 A KR1019940011508 A KR 1019940011508A KR 19940011508 A KR19940011508 A KR 19940011508A KR 950034693 A KR950034693 A KR 950034693A
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South Korea
Prior art keywords
tin
forming
layer
thin film
multilayer thin
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KR1019940011508A
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Korean (ko)
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KR0142796B1 (en
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변정수
곽병호
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문정환
엘지반도체 주식회사
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Priority to KR1019940011508A priority Critical patent/KR0142796B1/en
Priority to JP7151134A priority patent/JPH07326612A/en
Publication of KR950034693A publication Critical patent/KR950034693A/en
Application granted granted Critical
Publication of KR0142796B1 publication Critical patent/KR0142796B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 다층박막 금속배선에 관한 것으로, 특히 EM(Electro Migration)의 신뢰성이 우수한 반도체 다층박막 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor multilayer thin film metallization, and more particularly to a method for forming semiconductor multilayer thin film metallization with excellent reliability of EM (Electro Migration).

이에 본 발명의 다층박막 형성방법은 실리콘(Si) 웨이퍼상에 TiN1-x증착하고 열처리하여 보템 (bottom) TiN 층을 형성하는 공정, 상기 TiN 층위에 알루미늄(Al)층을 형성하는 공정, 상기 알루미늄(Al)층상에 탑(top) TiN 층을 형성하는 공정을 포함하여 이루어진다.In the method of forming a multilayer thin film of the present invention, a process of forming a bottom TiN layer by depositing and thermally treating TiN 1 - x on a silicon (Si) wafer, and forming an aluminum (Al) layer on the TiN layer, And forming a top TiN layer on the aluminum (Al) layer.

Description

반도체 다층박막 금속배선 형성방법Method of forming semiconductor multilayer thin film metal wiring

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 다층금속 박막 형성직후 특성 스펙트럼도, 제3도는 본 발명의 다층금속 박막을 열처리한 후 특성 스펙트럼도, 제4도는 본 발명에 따른 질소(N2)/아르곤(Ar) 유량비도.2 is a characteristic spectrum diagram immediately after formation of the multilayer metal thin film of the present invention, FIG. 3 is a characteristic spectrum diagram after heat treatment of the multilayer metal thin film of the present invention, and FIG. 4 is a flow rate ratio of nitrogen (N 2 ) / argon (Ar) according to the present invention. Degree.

Claims (5)

실리콘(Si) 웨이퍼상에 TiN1-x증착하고 열처리하여 보템(bottom) TiN 층을 형성하는 공정, 상기 TiN 층위에 알루미늄(Al) 층을 형성하는 공정, 상기 알루미늄(Al)층상에 탑(top) TiN 층을 형성하는 공정을 포함하여 이루어짐을 특성으로 하는 반도체 다층박막 금속배선 형성방법.Depositing TiN 1 - x on a silicon (Si) wafer and heat treatment to form a bottom TiN layer, forming an aluminum (Al) layer on the TiN layer, and forming a top on the aluminum (Al) layer ) A method for forming a semiconductor multilayer thin film metal wiring, comprising the step of forming a TiN layer. 제1항에 있어서, 보템 TiN 층, 알루미늄(Al)층, 탑 TiN 층 형성공정은, 진공단절 없이 연속증착함을 특징으로 하는 반도체 금속배선 형성방법.The method of claim 1, wherein the formation process of the botem TiN layer, the aluminum (Al) layer, and the top TiN layer is carried out continuously without vacuum breaking. 제1항에 있어서, TiN1-x증착시 질소(N2)의 유량비를 금속분위기(Metal Mode) 이하의 범위에서 티타늄(Ti) 함량이 많은 TiN을 증착하여 형성함을 특징으로 하는 반도체 다층박막 금속배선 형성방법.The semiconductor multilayer thin film according to claim 1, wherein the TiN 1 - x is formed by depositing TiN having a high Ti content in a flow rate ratio of nitrogen (N 2 ) at or below a metal atmosphere (Metal Mode). Metal wiring formation method. 제1항에 있어서, 열처리공정은 500。C~700。C로 질소(N2) 또는 암모니아 (NH3)분위기에서 열처리함을 특징으로 하는 반도체 다층박막 금속배선 형성방법.The method of claim 1, wherein the heat treatment is performed at 500 ° C. to 700 ° C. in a nitrogen (N 2 ) or ammonia (NH 3 ) atmosphere. 제1항 또는 제4항에 있어서, 열처리시 실리콘(Si) 표면에서는 111 배향성을 갖는 TiN/TiSi2이 형성되고, 산화실리콘(SiO2) 표면에서는 111 배향성을 갖는 TiN/Ti이 형성됨을 특징으로 하는 반도체 다층박막 금속배선 형성방법.The method of claim 1 or 4, wherein during heat treatment, TiN / TiSi 2 having 111 orientation is formed on the silicon (Si) surface, and TiN / Ti having 111 orientation is formed on the silicon oxide (SiO 2 ) surface. A method of forming a semiconductor multilayer thin film metal wiring. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940011508A 1994-05-26 1994-05-26 Method of forming the multilayng wiring on the semiconductor device KR0142796B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019940011508A KR0142796B1 (en) 1994-05-26 1994-05-26 Method of forming the multilayng wiring on the semiconductor device
JP7151134A JPH07326612A (en) 1994-05-26 1995-05-26 Wiring formation method for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940011508A KR0142796B1 (en) 1994-05-26 1994-05-26 Method of forming the multilayng wiring on the semiconductor device

Publications (2)

Publication Number Publication Date
KR950034693A true KR950034693A (en) 1995-12-28
KR0142796B1 KR0142796B1 (en) 1998-08-17

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KR1019940011508A KR0142796B1 (en) 1994-05-26 1994-05-26 Method of forming the multilayng wiring on the semiconductor device

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JP (1) JPH07326612A (en)
KR (1) KR0142796B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100386034B1 (en) 2000-12-06 2003-06-02 에이에스엠 마이크로케미스트리 리미티드 Method of Fabricating Semiconductor Device Employing Copper Interconnect Structure Having Diffusion Barrier Stuffed with Metal Oxide
JP6582537B2 (en) * 2015-05-13 2019-10-02 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03262127A (en) * 1990-03-13 1991-11-21 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JP2861583B2 (en) * 1992-01-17 1999-02-24 ヤマハ株式会社 Semiconductor device manufacturing method
JPH05198577A (en) * 1992-01-22 1993-08-06 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH0677161A (en) * 1992-08-25 1994-03-18 Oki Electric Ind Co Ltd Manufacture of semiconductor element

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KR0142796B1 (en) 1998-08-17
JPH07326612A (en) 1995-12-12

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