KR960032643A - Method for forming titanium silicide of dense titanium nitride film and dense titanium nitride film / thin film and manufacturing method of semiconductor device using same - Google Patents

Method for forming titanium silicide of dense titanium nitride film and dense titanium nitride film / thin film and manufacturing method of semiconductor device using same Download PDF

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KR960032643A
KR960032643A KR1019950002495A KR19950002495A KR960032643A KR 960032643 A KR960032643 A KR 960032643A KR 1019950002495 A KR1019950002495 A KR 1019950002495A KR 19950002495 A KR19950002495 A KR 19950002495A KR 960032643 A KR960032643 A KR 960032643A
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titanium
film
nitride film
forming
titanium nitride
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KR0156219B1 (en
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변정수
김학남
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문정환
Lg 반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

본 발명은 치밀한 티타늄 질화막 및 치밀한 티타늄 질화막/박막의 티타늄 실리사이드 형성방법 및 이를 이용한 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for forming titanium silicide of a dense titanium nitride film and a dense titanium nitride film / thin film and a method of manufacturing a semiconductor device using the same.

티타늄 질화막이 형성된 티타늄 타겟을 스퍼터링하여 반도체 기판상에 질소원자가 과량 함유된 티타늄막을 중착하고, 2회에 걸쳐 급속열처리하여 반도체 기판상에 박막의 티타늄 실리사이드와 치밀한 질화막을 형성한다.By sputtering a titanium target on which a titanium nitride film is formed, a titanium film containing an excess of nitrogen atoms is deposited on the semiconductor substrate, followed by rapid heat treatment twice to form a thin titanium silicide and a dense nitride film on the semiconductor substrate.

COB DRAM 소자의 비트라인을 텅스텐으로 제조하는 경우에 치밀한 티타늄 질화막/박막의 티타늄 실리사이드가 후속의 캐패시터 형성공정시 텅스텐의 고온확산을 방지하는 배리어로서 역할을 하여 콘택특성이 우수하고 배리어 특성이 보존된 우수한 텅스텐 비트라인을 형성한다.When the bit line of the COB DRAM device is made of tungsten, the dense titanium nitride / thick titanium silicide acts as a barrier to prevent high temperature diffusion of tungsten during the subsequent capacitor formation process. It forms an excellent tungsten bitline.

치밀한 티타늄 질화막/박막의 티타늄 실리사이드를 Al 배선에 이용시 콘택부에서는 티타늄 실리사이드가 형성되어 콘택특성을 향상시키고, 티타늄 질화막과 Al 배선간에는 TiAl3가 형성되어 금속배선의 전자이동(electromigration) 특성을 향상시킨다.When titanium silicide of dense titanium nitride / thin film is used for Al wiring, titanium silicide is formed at the contact portion to improve contact characteristics, and TiAl 3 is formed between the titanium nitride film and Al wiring to improve the electromigration characteristics of the metal wiring. .

Description

치밀한 티타늄 질화막 및 치밀한 티타늄 질화막/박막의 티타늄 실리사이드 형성방법 및 이를 이용한 반도체소자의 제조방법.A method of forming titanium silicide of a dense titanium nitride film and a dense titanium nitride film / thin film and a method of manufacturing a semiconductor device using the same.

제6도(A)와 (B)는 본 발명의 제1실시예에 따른 치밀한 티타늄막의 형성공정도,6 (A) and (B) are process charts for forming the dense titanium film according to the first embodiment of the present invention,

제7도(A)와 (B)는 본 발명의 제2실시예에 따른 치밀한 티타늄 질화막/박막의 티타늄 실리사이드의 형성공정도.7 (A) and (B) are process charts for forming the titanium silicide of the dense titanium nitride film / thin film according to the second embodiment of the present invention.

Claims (22)

티타늄 타겟을 준비하는 스텝과, 티타늄 타겟의 표면에 티타늄 질화막을 형성하는 스텝과, 반도체 기판의 표면에 산화막을 형성하는 스텝과, 티타늄 질화막이 형성된 티타늄 타겟을 스퍼터링하여 질소원자가 과량 함유된 티타늄막을 산화막상에 중착하는 스텝과, 질소원자가 과량 함유된 타타늄막을 급속열처리하여 산화막상에 치밀한 질화막을 형성하는 스텝을 포함하는 것을 특징으로 하는 치밀한 티타늄 질화막의 형성방법.Preparing a titanium target, forming a titanium nitride film on the surface of the titanium target, forming an oxide film on the surface of the semiconductor substrate, and sputtering a titanium target on which the titanium nitride film is formed to oxidize the titanium film containing excess nitrogen atoms. And forming a dense nitride film on the oxide film by rapidly heat-treating the titanium film containing excess nitrogen atoms on the film. 제1항에 있어서, 티타늄 질화막이 표면이 형성된 티타늄 타겟을 이용한 티타늄막의 중착은 순수한 아르곤 분위기에서 수행되어지는 것을 특징으로 하는 치밀한 티타늄 질화막의 형성방법.The method of forming a dense titanium nitride film according to claim 1, wherein the deposition of the titanium film using the titanium target on which the titanium nitride film is formed is carried out in a pure argon atmosphere. 제1항에 있어서, 상기 질소원자가 과량 함유된 티타늄막을 1~3회에 걸쳐 급속 열처리하는 것을 특징으로 하는 치밀한 티타늄 질화막의 형성방법.The method of forming a dense titanium nitride film according to claim 1, wherein the titanium film containing an excess of nitrogen atoms is rapidly heat treated one to three times. 제1항에 있어서, 상기 열처리공정은 500℃에서 40초동안 수행한 후 800℃에서 30초동안 수행되어지는 것을 특징으로 하는 치밀한 티타늄 질화막의 형성방법.The method of claim 1, wherein the heat treatment is performed at 500 ° C. for 40 seconds and then at 800 ° C. for 30 seconds. 제1항에 있어서, 티타늄막의 열처리공정은 N₂또는 NH₃분위기에서 수행되어지는 것을 특징으로 하는 치밀한 티타늄 질화막의 형성방법.The method of forming a dense titanium nitride film according to claim 1, wherein the heat treatment of the titanium film is performed in an N 2 or NH 3 atmosphere. 제1항에 있어서, 티타늄막중 질소원자가 과량 함유된 티타늄막은 티타늄 타겟의 표면에 형성된 티타늄 질화막의 두께에 대응하는 두께로 형성되는 것을 특징으로 하는 치밀한 티타늄 질화막의 형성방법.The method of claim 1, wherein the titanium film containing excess nitrogen atoms in the titanium film is formed to a thickness corresponding to the thickness of the titanium nitride film formed on the surface of the titanium target. 제6항에 있어서. 티타늄막에 질소원자는 5~45%의 양으로 포함되어 있는 것을 특징으로 하는 치밀한 티타늄 질화막의 형성방법.The method of claim 6. A method of forming a dense titanium nitride film, characterized in that the nitrogen film is contained in an amount of 5 to 45% in the titanium film. 제6항에 있어서, 총 티타늄막의 두께에 대한 티타늄막중 과량의 질소가 함유되어 있는 부분의 두께의 비는 0.05~0.95인 것을 특징으로 하는 치밀한 티타늄 질화막의 형성방법.The method of forming a dense titanium nitride film according to claim 6, wherein the ratio of the thickness of the portion containing the excess nitrogen to the total titanium film thickness is 0.05 to 0.95. 티타늄 타겟을 준비하는 스텝과, 티타늄 타겟의 표면에 티타늄 질화막을 형성하는 스텝과, 티타늄 질화막이 형성된 타타늄 타겟을 스퍼터링하여 반도체 기판상에 질소원자가 과량 함유된 티타늄막을 중착하는 스텝과, 질소원자가 과량 함유된 티타늄막을 급속열처리하여 반도체 기판상에 치밀한 티타늄 질화막을 형성하고, 반도체 기판과 치밀한 티타늄 질화막의 계면에는 박막의 티타늄 실리사이드를 형성하는 스텝을 포함하는 것을 특징으로 하는 치밀한 티타늄질화막/박막의 티타늄 실리사이드 형성방법.Preparing a titanium target, forming a titanium nitride film on the surface of the titanium target, sputtering a titanium target on which the titanium nitride film is formed, and depositing a titanium film containing an excess of nitrogen atoms on the semiconductor substrate; Rapid heat treatment of the excess titanium film to form a dense titanium nitride film on the semiconductor substrate, and at the interface between the semiconductor substrate and the dense titanium nitride film, a step of forming a thin titanium silicide, characterized in that the titanium titanium film / thin titanium Silicide formation method. 제9항에 있어서, 티타늄 질화막이 표면에 형성된 티타늄 타겟을 이용한 티타늄막의 중착온 순수한 아르곤 분위기에서 수행되어지는 것을 특징으로 하는 치밀한 티타늄 질화막/박막의 티타늄 실리사이드 형성방법.10. The method of claim 9, wherein the titanium nitride film is carried out in a solid argon atmosphere of a titanium film using a titanium target formed on the surface. 제9항에 있어서, 상기 질소원자가 과량 함유된 티타늄막을 2회에 걸쳐 급속열처리하는 것을 특징으로 하는 치밀한 티타늄 질화막/박막의 실리사이드 형성방법.10. The method of claim 9, wherein the titanium film containing excess nitrogen atoms is subjected to rapid heat treatment twice. 제11항에 있어서, 상기 열처리공정은 500℃에서 40초동안 수행한 후 800℃에서 30초동안 수행되어지는 것을 특징으로 하는 치밀한 티타늄 질화막/박막의 실리사이드 형성방법.12. The method of claim 11, wherein the heat treatment is performed for 40 seconds at 500 ° C and then for 30 seconds at 800 ° C. 제9항에 있어서, 티타늄막의 열처리공정은 N₂또는 NH₃분위기에서 수행되어지는 것을 특징으로 하는 치밀한 티타늄 질화막/박막의 티타늄 실리사이드 형성방법.10. The method of claim 9, wherein the heat treatment of the titanium film is carried out in an N 2 or NH 3 atmosphere. 제9항에 있어서, 티타늄막중 질소원자가 과량 함유된 부분은 티타늄 타겟의 표면에 형성된 티타늄 질화막의 두께에 대응하여 형성되는 것을 특징으로 하는 치밀한 티타늄 질화막/박막의 티타늄 실리사이드 형성방법.10. The method of claim 9, wherein an excess of nitrogen atoms in the titanium film is formed corresponding to the thickness of the titanium nitride film formed on the surface of the titanium target. 제14항에 있어서, 티타늄막에 질소원자는 5~45%의 양으로 포함되어 있는 것을 특징으로 하는 치밀한 티타늄 질화막/박막의 티타늄 실리사이드 형성방법.15. The method of claim 14, wherein the titanium film contains nitrogen atoms in an amount of 5 to 45%. 제14항에 있어서, 총 티타늄막의 두께에 대한 티타늄막중 과량의 질소가 함유되어 있는 부분의 두께의 비는 0.05~0.95인 것을 특징으로 하는 치밀한 티타늄질화막/박막의 실리사이드 형성방법.15. The method of claim 14, wherein the ratio of the thickness of the portion of the titanium film containing excess nitrogen to the total thickness of the titanium film is 0.05-0.95. 제1도전형의 반도체 기판상에 게이트 산화막을 형성하는 스텝과, 게이트 산화막상에 폴리실리콘막을 형성하는 스텝과, 티타늄 타겟을 준비하는 스텝과, 티타늄 타겟의 표면에 티타늄 질화막을 형성하는 스텝과, 티타늄 질화막이 형성된 티타늄 타겟을 스퍼터링하여 풀리실리콘막상에 질소원자가 과량 함유된 티타늄막을 증착하는 스텝과, 질소원자가 과량 함유된 티타늄막을 급속열처리하여 폴리실리콘막상에 박막의 치밀한 티타늄막을 형성하고 폴리실리콘막과 치밀한 질화막 사이에 박막의 티타늄 실리사이드를 형성하는 스텝과, 상기 티타늄 질화막, 티타늄 실리사이드 및 폴리실리콘막을 순차 패터닝하여 게이트를 형성하는 스텝과, 상기 게이트를 마스크로하여 기판으로 제2도전형의 불순물을 이온주입하여 불순물 영역을 형성하는 스텝을 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a gate oxide film on the first conductive semiconductor substrate, forming a polysilicon film on the gate oxide film, preparing a titanium target, forming a titanium nitride film on the surface of the titanium target, Sputtering the titanium target on which the titanium nitride film is formed to deposit a titanium film containing an excess of nitrogen atoms on the pulley silicon film, and rapidly heat-treating the titanium film containing an excess of nitrogen atoms to form a dense titanium film of thin film on the polysilicon film. Forming a thin film of titanium silicide between the dense nitride film, forming a gate by sequentially patterning the titanium nitride film, the titanium silicide and the polysilicon film, and ion-containing impurities of the second conductivity type to the substrate using the gate as a mask. Implanting to form impurity regions Method for manufacturing a semiconductor device, characterized in that. 제1도전형의 반도체 기판상에 제2도전형의 불순물 영역을 형성하는 스텝, 불순물 영역이 형성된 반도체 기판상에 절연막을 형성하는 스텝과, 상기 불순물 영역상부의 절연막을 제거하여 콘택홀을 형성하는 스텝과, 티타늄 타겟을 준비하는 스텝과, 티타늄 타겟의 표면에 티타늄 질화막을 형성하는 스텝과, 티타늄 질화막이 형성된 티타늄 타겟을 스퍼터링하여 질소원자가 과량 함유된 티타늄막을 기판전면에 걸쳐 증착하는 스텝과, 질소원자가 과량 함유된 티타늄막을 급속열처리하여 기판전면에 걸쳐 티타늄 질화막을 형성하고, 콘택홀내의 블순물 영역과 티타늄 질화막의 계면에는 박막의 티타늄 실리사이드를 형성하는 스텝과, 티타늄 질화막상에 비트라인용 금속층을 형성하는 스텝과, 상기 티타늄 질화막과 금속층을 순차 패터닝하여 콘택홀을 통해 불순물 영역과 접촉되도록 비트라인을 형성하는 스텝과, 통상의 캐패시터 형성공정을 수행하여 캐패시터를 형성하는 스텝을 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming an impurity region of the second conductivity type on the semiconductor substrate of the first conductivity type, forming an insulating film on the semiconductor substrate on which the impurity region is formed, and forming a contact hole by removing the insulating film on the impurity region. A step of preparing a titanium target, a step of forming a titanium nitride film on the surface of the titanium target, a step of sputtering a titanium target on which the titanium nitride film is formed, and depositing a titanium film containing excess nitrogen atoms over the entire surface of the substrate; Rapid heat treatment of the self-contained titanium film to form a titanium nitride film over the entire surface of the substrate, forming a thin film of titanium silicide at the interface between the impurities and the titanium nitride film in the contact hole, and a bit line metal layer on the titanium nitride film Forming and sequentially patterning the titanium nitride film and the metal layer through a contact hole And forming a bit line in contact with the impurity region, and forming a capacitor by performing a conventional capacitor forming step. 제18항에 있어서, 비트라인용 금속층이 텅스텐인 것을 특징으로 하는 반도체 소자의 제조방법.19. The method of manufacturing a semiconductor device according to claim 18, wherein the bit line metal layer is tungsten. 제18항에 있어서, 비트라인용 금속층을 화학적 중착법으로 중착하는 것을 특징으로 하는 반도체소자의 제조방법.19. The method of manufacturing a semiconductor device according to claim 18, wherein the bit line metal layer is subjected to chemical deposition. 제1도전형의 반도체 기판상에 제2도전형의 불순물 영역을 형성하는 스텝과, 불순물 영역이 형성된 반도체 기판상에 절연막을 형성하는 스텝과, 상기 불순물 영역상부의 절연막을 제거하여 콘택홀을 형성하는 스텝과 티타늄 타겟을 준비하는 스텝과, 티타늄 타겟의 표면에 티타늄 질화막을 형성하는 스텝과, 티타늄 질화막이 형성된 티타늄 타겟을 스퍼터링하여 질소원자가 과량 함유된 티타늄막을 기판전면에 걸쳐 증착하는 스텝과, 질소원자가 과량 함유된 티타늄막상에 금속배선용 알루미늄층을 고온에서 플로잉시켜 증착시킴과 동시에 기판전면에 걸쳐 티타늄 질화막을 형성하고, 불순물 영역과 티타늄 질화막의 계면에는 박막의 티타늄 실리사이드를 형성하는 스텝과, 상기 티타늄 질화막과 알루미늄층을 순차 패터닝하여 금속배선을 형성하는 스텝을 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a contact hole by forming an impurity region of a second conductivity type on the semiconductor substrate of the first conductivity type, forming an insulating film on the semiconductor substrate on which the impurity region is formed, and removing an insulating film on the impurity region. A step of preparing a titanium target, a step of forming a titanium nitride film on the surface of the titanium target, a step of sputtering a titanium target on which the titanium nitride film is formed, and depositing a titanium film containing an excess of nitrogen atoms over the entire surface of the substrate; Forming a titanium nitride film over the entire surface of the substrate by flowing an aluminum layer for metal wiring at a high temperature on the titanium film containing self excess; and forming a titanium silicide thin film at an interface between the impurity region and the titanium nitride film; A metal pattern is formed by sequentially patterning a titanium nitride film and an aluminum layer. A method for manufacturing a semiconductor device comprising a step. 제21항에 있어서, 상기 고온이 플로잉공정시 티타늄 질화막과 알루미늄층의 계면에서는 TiAl3가 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.22. The method of claim 21, wherein TiAl 3 is formed at the interface between the titanium nitride film and the aluminum layer during the high temperature flow step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
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KR100440467B1 (en) * 2001-11-12 2004-07-14 아남반도체 주식회사 Formation method of stacking structure of metal line in semiconductor device
KR100707668B1 (en) * 2005-12-27 2007-04-13 동부일렉트로닉스 주식회사 Metal stack structure of semiconductor device and fabrication method thereof
KR20200140925A (en) * 2018-05-04 2020-12-16 어플라이드 머티어리얼스, 인코포레이티드 Methods and apparatus for high reflectivity aluminum layers

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KR100872712B1 (en) * 2006-08-29 2008-12-09 동부일렉트로닉스 주식회사 Semiconductor device and Method for manufacturing thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100440467B1 (en) * 2001-11-12 2004-07-14 아남반도체 주식회사 Formation method of stacking structure of metal line in semiconductor device
KR100707668B1 (en) * 2005-12-27 2007-04-13 동부일렉트로닉스 주식회사 Metal stack structure of semiconductor device and fabrication method thereof
KR20200140925A (en) * 2018-05-04 2020-12-16 어플라이드 머티어리얼스, 인코포레이티드 Methods and apparatus for high reflectivity aluminum layers

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