KR950033870A - Control Method of Current Retry Count in Multiprocessor Interrupt Requestor - Google Patents

Control Method of Current Retry Count in Multiprocessor Interrupt Requestor Download PDF

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Publication number
KR950033870A
KR950033870A KR1019940010639A KR19940010639A KR950033870A KR 950033870 A KR950033870 A KR 950033870A KR 1019940010639 A KR1019940010639 A KR 1019940010639A KR 19940010639 A KR19940010639 A KR 19940010639A KR 950033870 A KR950033870 A KR 950033870A
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KR
South Korea
Prior art keywords
retry count
count value
current retry
interrupt
current
Prior art date
Application number
KR1019940010639A
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Korean (ko)
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KR960009662B1 (en
Inventor
모상만
원철호
심원세
윤석한
Original Assignee
양승택
재단법인 한국전자통신연구소
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Priority to KR94010639A priority Critical patent/KR960009662B1/en
Publication of KR950033870A publication Critical patent/KR950033870A/en
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Publication of KR960009662B1 publication Critical patent/KR960009662B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Abstract

본 발명은 다중프로세서 인터럽트 요청기에서의 현재 재시도 계수치 제어방법에 관한 것으로서, 본 발명에서는 프로세서간 인터럽트의 전송시 오류가 발생하여 전송을 재시도하는 경우에 재시도 회수를 제어하기 위하여 제어 및 상태 레지스터에 현재 재시도 계수치 항목을 두고, 초기상태인 IDLE 상태이고 프로세서간 인터럽트의 전송이 요구되고 인터럽트 버스가 유휴(Idle) 상태인 경우이면 최대 재시도 계수치의 값을 현재 재시도 계수치에 복사하고, CHECK 상태이고 전송오류가 발생하였고 유한 재시도 조건에서 재시도 회수가 만료되지 않은 경우이면 현재 재시도 계수치의 값을 1만큼 내림순으로 계수하여 현재 재시도 계수치를 제어할 수 있다.The present invention relates to a method of controlling a current retry count value in a multiprocessor interrupt requester. The present invention relates to a control and state in order to control the number of retries when an error occurs when retransmitting an interprocessor interrupt. If the current retry count value is placed in the register, and the initial IDLE state and the inter-processor interrupt transfer are required, and the interrupt bus is idle, the maximum retry count value is copied to the current retry count value. If the status is CHECK and a transmission error occurs and the number of retries has not expired under a finite retry condition, the current retry count can be controlled by counting the current retry count value in descending order.

Description

다중 프로세서 인터럽트 요청기에서의 현재 재시도 계수치 제어방법Control Method of Current Retry Count in Multiprocessor Interrupt Requestor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 다중프로세서 인터럽트 요청기의 연결도, 제2도는 다중프로세서 인터럽트 요청기의 내부 레지스터 구성도.1 is a connection diagram of a multiprocessor interrupt requester, and FIG. 2 is an internal register configuration diagram of a multiprocessor interrupt requester.

Claims (1)

다중프로세서 인터럽트 요청기(3)로 입력되는 클럭이 상승에지인가를 판단하여(단계 27) 아니면 반복하여 이 판단을 수행하는 단계와, 상기 판단(단계 27)에 의해서 클럭이 상승에지이면, 초기상태인 IDLE 상태이고 프로세서간 인터럽트의송신 및 완료비트(15)가 1이고 인터럽트 버스(5)가 유휴상태인가를 판단하여(단계 28)이 판단(단계 28)조건에 만족한다면 최대 재시도 계수치비트(8)의 값을 현재 재시도 계수치 비트(9)에 복사하고 단계(29) 상기 단계27로 복귀하는 단계와, 상기 판단(단계 28) 조건에 만족하지 않는다면, ACK 상태(24)에서 받은 응답정보를 검사하는 CHECK 상태(25)이면 전송오류(11)가 발생되고 유한 재시도 인에이블(13)이 비트가 1이고, 상기 전송오류(11)의 발새에 의한 현재 재시도 계수치(9)의 값이 0이 아닌가를 판단하여(단계 30)이 판단(단계 30) 조건에 만족한다면, 전송이 성공할 때까지 상기 현재 재시도 계수치(9)의값을 1만큼 감소시키고(단계 31) 상기 단계 27로 복귀하는 단계와, 상기 판단조건(단계 30)에 만족하지 않는다면, 상기 단계 27로 복귀하는 단계를 포함하는 다중프로세서 인터럽트 요청기에서의 현재 재시도 계수치 제어방법.Determining whether the clock input to the multiprocessor interrupt requester 3 is a rising edge (step 27) or repeatedly performing this determination; if the clock is rising edge by the determination (step 27), the initial state Is in the IDLE state and the transmission and completion bit 15 of the interprocessor interrupt is 1 and the interrupt bus 5 is determined to be idle (step 28), and if the condition is satisfied (step 28), the maximum retry count value bit ( Copying the value of 8) into the current retry count value bit 9 and returning to step 27 and step 27, and if the decision (step 28) condition is not satisfied, the response information received in the ACK state 24; If the CHECK state (25) to check the transmission error 11 is generated and the finite retry enable 13 is a bit 1, the value of the current retry count value (9) due to the arrival of the transmission error (11) Determine if this is not 0 (step 30) and determine (step 30) If the condition is satisfied, decreasing the value of the current retry count value 9 by 1 until the transmission is successful (step 31) and returning to the step 27, and if the determination condition (step 30) is not satisfied, And returning to step 27, the current retry count control method in a multiprocessor interrupt requester. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR94010639A 1994-05-16 1994-05-16 Control scheme of current retry count in a multiprocessor interrupt requester KR960009662B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR94010639A KR960009662B1 (en) 1994-05-16 1994-05-16 Control scheme of current retry count in a multiprocessor interrupt requester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR94010639A KR960009662B1 (en) 1994-05-16 1994-05-16 Control scheme of current retry count in a multiprocessor interrupt requester

Publications (2)

Publication Number Publication Date
KR950033870A true KR950033870A (en) 1995-12-26
KR960009662B1 KR960009662B1 (en) 1996-07-23

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