KR960001995A - Interrupt Transmission and Completion Control Method in Multiprocessor Interrupt Requestor - Google Patents

Interrupt Transmission and Completion Control Method in Multiprocessor Interrupt Requestor Download PDF

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Publication number
KR960001995A
KR960001995A KR1019940012744A KR19940012744A KR960001995A KR 960001995 A KR960001995 A KR 960001995A KR 1019940012744 A KR1019940012744 A KR 1019940012744A KR 19940012744 A KR19940012744 A KR 19940012744A KR 960001995 A KR960001995 A KR 960001995A
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KR
South Korea
Prior art keywords
interrupt
completion
transmission
multiprocessor
bit
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Application number
KR1019940012744A
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Korean (ko)
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KR970002400B1 (en
Inventor
모상만
원철호
김성운
윤석한
Original Assignee
양승택
재단법인한국전자통신연구소
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Priority to KR1019940012744A priority Critical patent/KR970002400B1/en
Publication of KR960001995A publication Critical patent/KR960001995A/en
Application granted granted Critical
Publication of KR970002400B1 publication Critical patent/KR970002400B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Abstract

본 발명은 다중프로세서 인터럽트 요청기에서의 인터럽트 송신 및 완료 제어방법에 관한 것으로서, 프로세서 간 인터럽트의 전송요구를 받고 이의 송신 및 전송완료를 제어하기 위하여 제어 및 상태 레지스터에 인터럽트 송신/완료비트를 두고, 제어 및 상태 레지스터의 최하위 바이트에 쓰기요구가 있으면 프로세서 인터페이스 회로와 다중 프로세서 인터럽트 요청기 사이의 데이타 버스의 최하의 비트를 인터럽트 송신/완료 비트에 기록하고, CKECK상태이고 전송오류가 발생하지 않았거나 또는 유한 재시도 조건에서 재시도 회수가 만료되었을 경우이면 인터럽트 송신/완료비트를 0으로 기록하여 프로세서간 인터럽트의 송신 및 전송완료를 제어하는 방법을 제공한다.The present invention relates to an interrupt transmission and completion control method in a multiprocessor interrupt requester, and includes an interrupt transmission / completion bit in a control and status register in order to receive an inter-processor interrupt request and control its transmission and completion. Write request to the least significant byte of the control and status register writes the least significant bit of the data bus between the processor interface circuit and the multiprocessor interrupt requester to the interrupt send / completion bit, and is in CKECK state and no transfer error occurred or When the number of retries has expired under a finite retry condition, an interrupt transmission / completion bit is recorded as 0 to provide a method for controlling the transmission and transmission completion of an interrupt between processors.

Description

다중프로세서 인터럽트 요청기에서의 인터럽트 송신 및 완료 제어방법(Control sheme of interrupt go and done in a multiprocessor interrupt requester)Control sheme of interrupt go and done in a multiprocessor interrupt requester

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 다중프로세서 인터럽트 요청기의 연결도.1 is a connection diagram of a multiprocessor interrupt requester.

제2도는 다중프로세서 인터럽트 요청기의 내부레지스터 구성도.2 is an internal register diagram of a multiprocessor interrupt requester.

제3도는 다중프로세서 인터럽트 요청기의 내부상태 천이의 개략도.3 is a schematic diagram of an internal state transition of a multiprocessor interrupt requester.

Claims (1)

다중프로세서 인터럽트 요청기(3)로 들어오는 입력클럭이 상승에지인가를 판단하여(단계 27) 상승에지 상태가 아니면 상승에지 상태가 될 때까지 반복하는 단계와, 상기 판단(단계 27)에 의해서 상기 입력클럭이 상승에지 상태이면 프로세서간 인터럽트의 전송요구에 대하여 이 전송요구의 송신 및 완료를 제어하기 위해서 제어 및 상태 레지스터CSR(7)의 최하위 비트에 쓰기 요구가 있는가를 판단하여(단계 28), 쓰기 요구가 있으면 프로세서 인터페이스 회로(2)와 다중프로세서 인터럽트 요청기(3) 사이의 데이터 버스의 최하위 비트(DATA[0])를 인터럽트 송신/완료비트인 CSR[0](15)에 기록하고(단계 29) 상기 단계 27로 복귀하는 단계와, 상기 판단(단계 28)에 의해서 쓰기요구가 없으면 CHECK 상태이고 전송오류를 나타내는 CSR(11)이 0이거나 또는 유한 재시도 인에이블을 나타내는 CSR(13)가 1이고 현재 재시도 계수치인 CSR(9)의 값이 0인가를 판단하여(단계 30), 이 판단의 조건을 만족하지 않는다면 상기 단계 27로 복귀하는 단계와, 상기 판단(단계 30)의 조건에 만족한다면 인터럽트 송신/완료비트인 CSR(15)을 전송 완료를 나타내는 0으로 기록하고(단계 31) 상기 단계 27로 복귀하는 단계를 포함하는 다중프로세서 인터럽트 요청기에서의 인터럽트 송신 및 완료 제어방법.It is determined whether the input clock coming into the multiprocessor interrupt requester 3 is the rising edge (step 27), and if it is not the rising edge state, the method is repeated until the rising edge state is reached, and the input is determined by the determination (step 27). If the clock is in the rising edge state, it is determined whether there is a write request in the least significant bit of the control and status register CSR7 in order to control the transmission and completion of the transfer request for the interprocessor interrupt transfer request (step 28). If present, the least significant bit (DATA [0]) of the data bus between the processor interface circuit (2) and the multiprocessor interrupt requester (3) is written to the interrupt send / completion bit, CSR [0] (15) (step 29). Returning to step 27, and if there is no write request by the decision (step 28), the CSR 11 indicating a CHECK state and indicating a transmission error is 0 or a finite retry enable. Determining whether the value of CSR9, which is 1, and the current retry count value is 0 (step 30), and if the condition of this judgment is not satisfied, returning to step 27; If the condition of (step 30) is satisfied, the interrupt sending / completion bit is written to zero indicating the completion of the transmission (step 31) (step 31) and an interrupt in the multiprocessor interrupt requester comprising returning to step 27 above. Transmission and completion control method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940012744A 1994-06-07 1994-06-07 Control scheme of interrupt go and done in a multiprocessor interrupt requester KR970002400B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940012744A KR970002400B1 (en) 1994-06-07 1994-06-07 Control scheme of interrupt go and done in a multiprocessor interrupt requester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940012744A KR970002400B1 (en) 1994-06-07 1994-06-07 Control scheme of interrupt go and done in a multiprocessor interrupt requester

Publications (2)

Publication Number Publication Date
KR960001995A true KR960001995A (en) 1996-01-26
KR970002400B1 KR970002400B1 (en) 1997-03-05

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021029514A1 (en) * 2019-08-12 2021-02-18 신영환 Dual blade blower

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021029514A1 (en) * 2019-08-12 2021-02-18 신영환 Dual blade blower

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